Method of forming metal interconnection using plating and semiconductor device manufactured by the method

Abstract

A method is provided for forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing process. A semiconductor device manufactured by this method is also provided. In the method of forming a metal interconnection, a recess region is formed in a portion of an insulation layer formed over a substrate, i.e., where a metal interconnection layer will be formed. A diffusion prevention layer is formed over the substrate, the insulation layer, and the recess region. Then, a metal seed layer is formed over the diffusion prevention layer only in the recess region using a chemical mechanical polishing process or an etch back process. A conductive plating layer is then formed on the metal seed layer only in the recess region. Thereafter, surface planarization is performed to form a metal interconnection layer in the recess region. The plating layer may be formed after forming the seed layer only in the bottom portion of the recess region.

What is claimed is:  
     
         1 . A method of forming a metal interconnection, the method comprising: 
 forming an insulation region on a substrate;    forming a recess region in the insulation layer;    forming a diffusion prevention layer over insulation layer and the recess region;    forming a metal seed layer over the diffusion prevention layer only in the recess region; and    forming a conductive plating layer on the seed layer using plating process.    
     
     
         2 . A method of forming a metal interconnection, as recited in  claim 1 , wherein the recess region comprises a trench region of a line shape having a predetermined depth from a top surface of the insulation layer.  
     
     
         3 . A method of forming a metal interconnection, as recited in  claim 1 , wherein the recess region, comprises: 
 a trench region of a line shape having a predetermined depth from the surface of the insulation layer; and    a contact hole region passing through the insulation layer.    
     
     
         4 . A method of forming a metal interconnection, as recited in  claim 1 , wherein forming the metal seed layer further comprises: 
 forming a preliminary seed layer over the diffusion prevention layer; and    removing a first portion of the preliminary seed layer outside of the recess region such that a second portion of the preliminary seed layer in the recess region forms the metal seed layer.    
     
     
         5 . A method of forming a metal interconnection, as recited in  claim 4 , wherein forming the preliminary seed layer is performed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method.  
     
     
         6 . A method of forming a metal interconnection, as recited in  claim 4 , wherein removing a first portion of the preliminary seed layer is performed by a chemical mechanical polishing (CMP) process.  
     
     
         7 . A method of forming a metal interconnection, as recited in  claim 6 , wherein a slurry used for the chemical mechanical polishing (CMP) process does not contain abrasives.  
     
     
         8 . A method of forming a metal interconnection, as recited in  claim 6 , wherein the chemical-mechanical polishing (CMP) process uses a slurry having a polishing selection ratio of 10:1-1000:1 with respect to the preliminary seed layer and the diffusion prevention layer.  
     
     
         9 . A method of forming a metal interconnection, as recited in  claim 4 , 
 wherein removing a first portion of the preliminary seed layer leaves the second portion of the preliminary seed layer and a third portion of the preliminary seed layer in the recess region, and    further comprising performing a wet etching process on the third portion of the preliminary seed layer to remove the third portion of the seed layer from the recess region.    
     
     
         10 . A method of forming a metal interconnection, as recited in  claim 9 , wherein the wet etching process is time-controlled.  
     
     
         11 . A method of forming a metal interconnection, as recited in  claim 10 , wherein the second portion of the preliminary seed layer is formed only on a bottom surface of the recess region.  
     
     
         12 . A method of forming a metal interconnection, as recited in  claim 4 , wherein removing a first portion of the preliminary seed layer further comprises: 
 forming an intermediate material layer over the preliminary seed layer to fill the recess region;    etching back and removing a first portion of the intermediate material layer and the first portion of the preliminary seed layer until a portion of the diffusion prevention layer outside the recess region is exposed; and    removing a second portion of the intermediate material layer remaining in the recess region.    
     
     
         13 . A method of forming a metal interconnection, as recited in  claim 12 , wherein the intermediate material layer comprises a photoresist material.  
     
     
         14 . A method of forming a metal interconnection, as recited in  claim 1 , further comprising performing a surface planarization process on the conductive plating layer and the diffusion prevention layer to expose a top surface of the insulation layer and to form a metal interconnection layer in the recess region.  
     
     
         15 . A method of forming a metal interconnection, as recited in  claim 14 , wherein the surface planarization is performed by a chemical mechanical polishing process using a slurry having nearly the same polishing speeds with respect to the diffusion prevention layer and the plating layer.  
     
     
         16 . A semiconductor device comprising: 
 a substrate;    an insulation layer formed over the substrate, the insulation layer having a recess region is formed in it;    a diffusion prevention layer formed over the insulation layer and in the recess region;    a metal seed layer formed over the diffusion prevention layer and in the recess region; and    a metal interconnection layer formed in the recess region on the metal seed layer therein.    
     
     
         17 . A semiconductor device, as recited in  claim 16 , wherein the recess region comprises a trench region of a line shape having a predetermined depth from the surface of the insulation layer, and the metal seed layer is formed over a bottom portion of the trench region.  
     
     
         18 . A semiconductor device, as recited in  claim 16 , 
 further comprising a lower conductive layer formed over the substrate,    wherein the recess region comprises a contact hole region that passes through the insulation layer and exposes the lower conductive layer,    wherein the diffusion prevention layer is formed in the contact hole region and over the lower conductive layer, and    wherein the metal seed layer is formed over the bottom portion of the contact hole.    
     
     
         19 . A semiconductor device, as recited in  claim 18 , wherein the recess region further comprises a trench region of a line shape having a predetermined depth from the surface of the insulation layer.  
     
     
         20 . A semiconductor device, as recited in  claim 19 , wherein the metal seed layer is formed over a bottom portion of the contact hole and a bottom portion of the trench region.  
     
     
         21 . A semiconductor device, as recited in  claim 16 , wherein the diffusion prevention layer comprises a material selected from the group consisting of a tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi 2 ), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), cobalt (Co), cobalt silicide (CoSi 2 ), and a composite layer comprising at least two of these materials.  
     
     
         22 . A semiconductor device, as recited in  claim 16 , wherein the metal seed layer comprises a material selected from the transition metal group of copper, platinum, palladium, rubidium, strontium, rhodium, and cobalt.  
     
     
         23 . A semiconductor device, as recited in  claim 22 , wherein the metal seed layer and the metal interconnection layer both comprise copper.