Methods and systems for designing integrated circuit gate arrays

Abstract

Methods of designing integrated circuit gate arrays include the step of generating a netlist for a gate array integrated circuit having at least first logic and signal resources therein, directly from bitstream data which characterizes a programmable logic device having a first operational functionality and the first logic and signal resources as well. The generating step is also followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first functionality. A preferred integrated circuit design system is also provided and includes a programmable logic device having pre-programmed logic and signal resources therein and a gate array device having base logic and signal resources therein which are equivalent to the unprogrammed logic and signal resources of the programmable logic device. A computer-based apparatus is also provided for decoding a bitstream that characterizes the programmable logic device having a first operational functionality when programmed, into a netlist that designates electrical connections in the gate array device when wired to have the first operational functionality, and to provide a method for generating scan-based test vectors to verify the first functionality. Accordingly, when switching from a functional programmable logic device (PLD) implementation to a gate array implementation, it is unnecessary to start the design process over from scratch by performing logic synthesis, place and route and other front end design operations associated with conventional gate array design techniques.

That which is claimed is:  
     
         1 . A method of designing an integrated circuit device, comprising the step of: 
 generating a netlist for a gate array integrated circuit having first logic and signal resources, from bitstream data which characterizes a programmable logic device having the first logic and signal resources.    
     
     
         2 . The method of  claim 1 , wherein the bitstream data characterizes a programmable logic device having a first operational functionality; and wherein said generating step is followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first operational functionality.  
     
     
         3 . The method of  claim 2 , wherein said generating step comprises determining end points of at least one net in the netlist directly from at least one bit of the bitstream data.  
     
     
         4 . The method of  claim 2 , wherein said generating step comprises generating a netlist for a gate array integrated circuit from bitstream data and programmable logic device definition data.  
     
     
         5 . The method of  claim 4 , wherein said generating step comprises determining end points of at least one net in the netlist directly from at least one bit of the bitstream data and the programmable logic device definition data.  
     
     
         6 . An integrated circuit design system, comprising: 
 a programmable logic device having pre-programmed logic and signal resources;    a gate array device having pre-wired logic and signal resources which are equivalent to the pre-programmed logic and signal resources of said programmable logic device; and    means for decoding a bitstream that characterizes said programmable logic device having a first operational functionality when programmed, into a netlist that designates electrical connections in said gate array device when wired to have the first operational functionality.    
     
     
         7 . A method of designing an integrated circuit device, comprising the step of: 
 generating a netlist for a gate array integrated circuit having a first operational functionality, from bitstream data which characterizes a programmable logic device having the first operational functionality.    
     
     
         8 . The method of  claim 7 , wherein said generating step comprises generating a netlist for a gate array integrated circuit having a first operational functionality, directly from bitstream data which characterizes a programmable logic device having the first operational functionality.  
     
     
         9 . The method of  claim 8 , wherein the netlist is generated from bitstream data and programmable logic device definition data.  
     
     
         10 . The method of  claim 8 , wherein the netlist is used to generate test vectors to be used for a test of operational functionality of said gate array integrated circuit.  
     
     
         11 . The method of  claim 10 , wherein said test of operational functionality includes scan-based testing.  
     
     
         12 . The method of  claim 9 , wherein the netlist is generated from bitstream data, programmable logic device definition data and gate array device definition data.  
     
     
         13 . A method of designing an integrated circuit device, comprising the step of: 
 generating hookup data which characterizes a plurality of nets for a gate array integrated circuit having a first operational functionality, from bitstream data which characterizes a programmable logic device having the first operational functionality.    
     
     
         14 . The method of  claim 13 , wherein said generating step comprises generating hookup data which characterizes a plurality of nets for a gate array integrated circuit having a first operational functionality, directly from bitstream data which characterizes a programmable logic device having the first operational functionality.  
     
     
         15 . The method of  claim 14 , wherein said generating step comprises generating hookup data for a gate array integrated circuit having a first operational functionality without synthesizing logic for the gate array integrated circuit.  
     
     
         16 . The method of  claim 14 , wherein said generating step comprises generating hookup data for a gate array integrated circuit having a first operational functionality and logic resource placement that is the same as the programmable logic device.  
     
     
         17 . The method of  claim 14 , wherein said generating step comprises generating hookup data for a gate array integrated circuit having a first operational functionality and signal path resources which are the same as the programmable logic device.  
     
     
         18 . The method of  claim 14 , wherein hookup coordinates are generated from the hookup data, said hookup coordinates defining connection points of at least two nets.  
     
     
         19 . The method of  claim 18 , further comprising the step of forming a first set of electrical connections between the at least two nets on the gate array integrated circuit; and wherein the locations of the first set of electrical connections are defined by the hookup coordinates.  
     
     
         20 . The method of  claim 19 , wherein said step of forming a first set of electrical connections comprises the use of a targeting energy beam.  
     
     
         21 . The method of  claim 19 , wherein said step of forming a first set of electrical connections comprises the use of a photomask which contains a pattern thereon having a location designated by the hookup coordinates.