Master-slave latch circuit for multithreaded processing

Abstract

A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in multiple modes, including a scan mode for testing purposes.

What is claimed is:  
     
         1 . A master-slave latch circuit for use in a multithreaded processor, comprising: 
 a plurality of master elements, each master element storing a state corresponding to a respective thread supported by said multithreaded processor;    selection logic coupled to the outputs of said master elements, said selection logic selecting a single one of said outputs of said master elements in response to a thread designation input; and    a common slave element coupled to said selection logic, said common slave element receiving as input and storing the selected single one of said outputs of said master elements.    
     
     
         2 . The master-slave latch circuit for use in a multithreaded processor of  claim 1 , wherein each said master element stores a state corresponding to a respective thread at times determined by a first phase of a common clock signal, and wherein said common slave element stores said selected single one of said outputs of said master elements at times determined by a second phase of said common clock signal, said second phase being different from said first phase.  
     
     
         3 . The master-slave latch circuit for use in a multithreaded processor of  claim 1 , wherein said thread designation input designates the currently active thread of said multithreaded processor.  
     
     
         4 . The master-slave latch circuit for use in a multithreaded processor of  claim 1 , wherein said plurality of master elements function as master elements during a first mode of operation, and wherein at least one of said master elements functions alternatively as a slave element during a second mode of operation.  
     
     
         5 . The master-slave latch circuit for use in a multithreaded processor of  claim 1 , wherein each said master element and said common slave element comprise a respective pair of inverters, the output of a first inverter of each pair driving the input of a second inverter of each pair, and the output of the second inverter driving the input of the first inverter.  
     
     
         6 . A multithreaded processor supporting concurrent processing of a plurality of threads, comprising: 
 at least one register for storing data for each of said plurality of threads, said register comprising a plurality of master-slave latch circuits, each master-slave latch circuit comprising: 
 (a) a plurality of master elements, each master element storing a state corresponding to a respective thread supported by said multithreaded processor;  
 (b) selection logic coupled to the outputs of said master elements, said selection logic selecting a single one of said outputs of said master elements in response to a thread designation input; and  
 (c) a common slave element coupled to said selection logic, said common slave element receiving as input and storing the selected single one of said outputs of said master elements.  
   
     
     
         7 . The multithreaded processor of  claim 6 , wherein each said master element stores a state corresponding to a respective thread at times determined by a first phase of a common clock signal, and wherein said common slave element stores said selected single one of said outputs of said master elements at times determined by a second phase of said common clock signal, said second phase being different from said first phase.  
     
     
         8 . The multithreaded processor of  claim 6 , wherein said thread designation input designates the currently active thread of said multithreaded processor.  
     
     
         9 . The multithreaded processor of  claim 6 , wherein said processor supports first and second modes of operation, and wherein said plurality of master elements function as master elements during said first mode of operation, and wherein at least one of said master elements functions alternatively as a slave element during said second mode of operation.  
     
     
         10 . The multithreaded processor of  claim 6 , wherein each said master element and said common slave element comprise a respective pair of inverters, the output of a first inverter of each pair driving the input of a second inverter of each pair, and the output of the second inverter driving the input of the first inverter.  
     
     
         11 . The multithreaded processor of  claim 6 , wherein said multithreaded processor supports fine-grained multithreading.  
     
     
         12 . The multithreaded processor of  claim 6 , wherein said multithreaded processor supports coarse-grained multithreading.  
     
     
         13 . A computer system for supporting hardware multithreading, comprising: 
 a memory for storing instructions and data for a plurality of threads;    at least one multithreaded processor communicating with said memory and supporting concurrent processing of a plurality of threads, said processor having at least one register for storing data for each of said plurality of threads, said register comprising a plurality of master-slave latch circuits, each master-slave latch circuit comprising: 
 (a) a plurality of master elements, each master element storing a state corresponding to a respective thread supported by said multithreaded processor;  
 (b) selection logic coupled to the outputs of said master elements, said selection logic selecting a single one of said outputs of said master elements in response to a thread designation input; and  
 (c) a common slave element coupled to said selection logic, said common slave element receiving as input and storing the selected single one of said outputs of said master elements.  
   
     
     
         14 . The computer system of  claim 13 , wherein each said master element stores a state corresponding to a respective thread at times determined by a first phase of a common clock signal, and wherein said common slave element stores said selected single one of said outputs of said master elements at times determined by a second phase of said common clock signal, said second phase being different from said first phase.  
     
     
         15 . The computer system of  claim 13 , wherein said thread designation input designates the currently active thread of said multithreaded processor.  
     
     
         16 . The computer system of  claim 13 , wherein said multithreaded processor supports coarse-grained multithreading.  
     
     
         17 . A multi-stage latch circuit for use in a multithreaded processor, comprising: 
 a first stage having a plurality of first stage memory elements, each first stage memory element corresponding to a respective thread supported by said multithreaded processor, each said first stage memory element storing a state corresponding to a respective input at times determined by a first phase of a clock signal;    selection logic coupled to the outputs of said first stage memory elements, said selection logic selecting a single one of said outputs of said first stage memory elements in response to a thread designation input; and    a common second stage memory element coupled to said selection logic and receiving as input the selected single one of said outputs of said first stage memory elements, said common second stage memory element storing a state corresponding to said selected single one of said outputs of said first stage memory elements at times determined by a second phase of said clock signal, said second phase being different from said first phase.    
     
     
         18 . The multi-stage latch circuit of  claim 17 , wherein said thread designation input designates the currently active thread of said multithreaded processor.