Latched address multi-chunk write to EEPROM

Abstract

An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

What is claimed is:  
     
         1 . A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays, comprising: 
 a plurality of address latches,    a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays,    means for storing subarray addresses into selected ones of said plurality of address latches, and storing data to be written into subarray locations indicated by said subarray addresses, into selected ones of said plurality of data registers, and    means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches.    
     
     
         2 . The circuit as recited in  claim 1 , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides, and said storing means includes means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits.  
     
     
         3 . The circuit as recited in  claim 2 , wherein individual ones of said plurality of subarray addresses are further coded such that a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits, and said plurality of address latches include a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits.  
     
     
         4 . The circuit as recited in  claim 3 , wherein said storing means includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits.  
     
     
         5 . The circuit as recited in  claim 4 , wherein said plurality of column address latches are individually dedicated to storing column addresses of a corresponding one of said plurality of EEPROM subarrays.  
     
     
         6 . The circuit as recited in  claim 5 , wherein said plurality of row address latches are individually dedicated to storing row addresses of a corresponding pair of said plurality of EEPROM subarrays.  
     
     
         7 . The circuit as recited in  claim 1 , wherein said plurality of address latches include a row address latch, and said plurality of EEPROM subarrays include a pair of EEPROM subarrays sharing said row address latch.  
     
     
         8 . An EEPROM chip comprising: 
 a plurality of EEPROM subarrays, and    a circuit for concurrently writing data into selected memory locations of said plurality of EEPROM subarrays, said circuit including, 
 a plurality of address latches,  
 a plurality of data registers individually coupled to a corresponding one of said-plurality of EEPROM subarrays,  
 means for storing subarray addresses into selected ones of said plurality of address latches, and storing data to be written into subarray locations indicated by said subarray addresses,, into selected ones of said plurality of data registers, and  
 means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches.  
   
     
     
         9 . The EEPROM chip as recited in  claim 8 , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides, and said storing means includes means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits.  
     
     
         10 . The EEPROM chip as recited in  claim 9 , wherein individual ones of said plurality of subarray addresses are further coded such that a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits, and said plurality of address latches include a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits.  
     
     
         11 . The EEPROM chip as recited in  claim 10 , wherein said storing-means includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits.  
     
     
         12 . The EEPROM chip as recited in  claim 11 , wherein said plurality of column address latches are individually dedicated to storing column addresses of a corresponding one of said plurality of EEPROM subarrays.  
     
     
         13 . The EEPROM chip as recited in  claim 12 , wherein said plurality of row address latches are individually dedicated to storing row addresses of a corresponding pair of said plurality of EEPROM subarrays.  
     
     
         14 . The EEPROM chip as recited in  claim 9 , wherein said plurality of address latches include a row address latch, and said plurality of EEPROM subarrays include a pair of EEPROM subarrays sharing said row address latch.  
     
     
         15 . A method of concurrently writing a plurality of data chunks into an EEPROM, comprising the steps of: 
 storing said plurality of data chunks into a plurality of data storage means respectively coupled to corresponding subarrays of said EEPROM;    providing row and column select signals to row and column decoder means coupled to said corresponding subarrays of said EEPROM; and    concurrently writing said plurality of data chunks stored in said plurality of data storage means into subarray locations of said corresponding subarrays of said EEPROM as indicated by said row and column select signals.    
     
     
         16 . The method as recited in  claim 15 , wherein said data chunks storing step comprises the step of sequentially storing said plurality of data chunks into said plurality of data storage means.  
     
     
         17 . The method as recited in  claim 16 , wherein said data chunks sequentially storing step comprises the steps of: 
 sequentially receiving a plurality of subarray addresses indicative of subarray locations wherein corresponding data chunks of said plurality of data chunks are to be written; and    sequentially storing said corresponding data chunks into said plurality of data storage means such that individual ones of said corresponding data chunks are stored in the data storage means coupled to the subarray including the subarray location indicated by the subarray address corresponding to said individual one data chunk.    
     
     
         18 . The method as recited in  claim 17 , wherein said row and column select signals providing step, comprises the steps of: 
 decoding individual ones of said plurality of addresses to determine the subarray location indicated by said individual one address; and    generating said row and column select signals from the decoded subarray locations of individual ones of said plurality of addresses.