Copper wiring module control

Abstract

Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties. Examples of the wafer properties that may be measured at the first process include thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity. Examples of the wafer properties that may be measured at the second process include copper clearing time, reflectance, thickness, and an electrical property.

We claim:  
     
         1 . A method for controlling an output property during wafer processing in a copper wiring module, said method comprising the steps of: 
 (1) measuring plating wafer property information during or after processing by a plating process;    (2) feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;    (3) measuring polishing wafer property information during or after processing by said polishing process; and    (4) optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.    
     
     
         2 . The method of  claim 1 , wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.  
     
     
         3 . The method of  claim 1 , further comprising: 
 measuring wafer property information during or after processing by one or more upstream wafer processing processes; and    further optimizing said polishing process by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing process.    
     
     
         4 . The method of  claim 3 , wherein said one or more upstream wafer processing processes comprises at least one of an etch or dielectric deposition process.  
     
     
         5 . The method of  claim 3 , wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.  
     
     
         6 . The method of  claim 1 , wherein said one or more target parameters of said polishing process comprises a removal rate parameter.  
     
     
         7 . The method of  claim 1 , wherein said one or more target parameters of said polishing process comprises a removal rate parameter and a bulk polish time.  
     
     
         8 . The method of  claim 1 , said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.  
     
     
         9 . The method of  claim 1 , said polishing wafer property information comprises copper clearing time, reflectance, thickness, and an electrical property.  
     
     
         10 . The method of  claim 1 , wherein said polishing process comprises a bulk polish process, an endpoint process, and a barrier polish process.  
     
     
         11 . The method of  claim 10 , wherein said polishing wafer property information comprises thickness profile information collected during or after said bulk polish process.  
     
     
         12 . The method of  claim 10 , wherein said polishing wafer property information comprises copper clearing information collected during or after said endpoint process.  
     
     
         13 . The method of  claim 10 , wherein said polishing wafer property information comprises an electrical property collected during or after said barrier polish process.  
     
     
         14 . The method of  claim 1 , wherein said polishing process comprises a chemical mechanical polishing process and said plating process comprises an electro chemical plating process.  
     
     
         15 . A copper wiring module for processes wafers, said copper wiring module comprising: 
 a plating tool for applying a plating to a wafer;    a first metrology device for measuring plating wafer property information during or after processing by the plating tool;    a polishing tool for polishing the wafer via at least one copper removal step;    a second metrology device for measuring plating wafer property information during or after processing by the polishing tool; and    a controller for optimizing processing of the polishing tool by using at least one of said plating wafer property information received from said first metrology device and said polishing wafer property information received from said second metrology device to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.    
     
     
         16 . The system of  claim 15 , wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.  
     
     
         17 . The system of  claim 15 , further comprising: 
 one or more upstream wafer processing tools;    a third metrology device for measuring wafer property information during or after processing by said one or more upstream wafer processing tools; and    wherein said controller further optimizes processing of said polishing tool by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing tool.    
     
     
         18 . The system of  claim 17 , wherein said one or more upstream wafer processing tools comprises at least one of an etch or dielectric deposition tool.  
     
     
         19 . The system of  claim 17 , wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.  
     
     
         20 . The system of  claim 15 , wherein said one or more target parameters of said polishing tool comprises a removal rate parameter.  
     
     
         21 . The system of  claim 15 , wherein said one or more target parameters of said polishing tool comprises a removal rate parameter and a bulk polish time.  
     
     
         22 . The system of  claim 15 , said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.  
     
     
         23 . The system of  claim 15 , wherein said polishing tool further comprises a bulk polish chamber, an endpoint chamber, and a barrier polish chamber.  
     
     
         24 . The system of  claim 23 , wherein said polishing wafer property information comprises thickness profile information collected at said bulk polish chamber.  
     
     
         25 . The system of  claim 23 , wherein said polishing wafer property information comprises copper clearing information collected at said endpoint chamber.  
     
     
         26 . The system of  claim 23 , wherein said polishing wafer property information comprises an electrical property collected at said barrier polish chamber.  
     
     
         27 . The system of  claim 15 , wherein said plating tool comprises an electro chemical plating tool and said polishing tool comprises a chemical mechanical polishing tool.  
     
     
         28 . An optimizer for optimizing processing of a copper wiring module, said optimizer comprising: 
 a communications port for receiving plating wafer property information received from a first metrology device associated with a plating tool and polishing wafer property information received from a second metrology device associated with a polishing tool;    a memory for storing tool recipes used to control operation of said plating tool and said polishing tool; and    a controller for optimizing processing of said polishing tool by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of a polishing tool recipe to obtain a desired output property on a wafer.    
     
     
         29 . A system for controlling an output property during wafer processing in a copper wiring module, said system comprising: 
 means for measuring plating wafer property information during or after processing by a plating process;    means for feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;    means for measuring polishing wafer property information during or after processing by said polishing process; and    means for optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.    
     
     
         30 . The system of  claim 29 , wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.  
     
     
         31 . The system of  claim 29 , further comprising: 
 means for measuring wafer property information during or after processing by one or more upstream wafer processing processes; and    means for further optimizing said polishing process by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing process.    
     
     
         32 . The system of  claim 31 , wherein said one or more upstream wafer processing processes comprises at least one of an etch or dielectric deposition process.  
     
     
         33 . The system of  claim 31 , wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.  
     
     
         34 . The system of  claim 29 , wherein said one or more target parameters of said polishing process comprises a removal rate parameter.  
     
     
         35 . The system of  claim 29 , wherein said one or more target parameters of said polishing process comprises a removal rate parameter and a bulk polish time.  
     
     
         36 . The system of  claim 29 , said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.  
     
     
         37 . The system of  claim 29 , said polishing wafer property information comprises copper clearing time, reflectance, thickness, and an electrical property.  
     
     
         38 . The system of  claim 29 , wherein said polishing process comprises a bulk polish process, an endpoint process, and a barrier polish process.  
     
     
         39 . The system of  claim 38 , wherein said polishing wafer property information comprises thickness profile information collected during or after said bulk polish process.  
     
     
         40 . The system of  claim 38 , wherein said polishing wafer property information comprises copper clearing information collected during or after said endpoint process.  
     
     
         41 . The system of  claim 38 , wherein said polishing wafer property information comprises an electrical property collected during or after said barrier polish process.  
     
     
         42 . The system of  claim 39 , wherein said plating process comprises an electro chemical plating process and said polishing process comprises a chemical mechanical polishing process.  
     
     
         43 . An optimizer for optimizing processing of a copper wiring module, said optimizer comprising: 
 means for receiving plating wafer property information received from a first metrology device associated with a plating tool and polishing wafer property information received from a second metrology device associated with a polishing tool;    means for storing tool recipes used to control operation of said plating tool and said polishing tool; and    means for optimizing processing of said polishing tool by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of a polishing tool recipe to obtain a desired output property on a wafer.    
     
     
         44 . A computer readable medium for controlling an output property during wafer processing in a copper wiring module, said computer readable medium comprising: 
 computer readable instructions for measuring plating wafer property information during or after processing by a plating process;    computer readable instructions for feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;    computer readable instructions for measuring polishing wafer property information during or after processing by said polishing process; and    computer readable instructions for optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.    
     
     
         45 . The computer readable medium of  claim 44 , wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.  
     
     
         46 . The computer readable medium of  claim 44 , further comprising: 
 computer readable instructions for measuring wafer property information during or after processing by one or more upstream wafer processing processes; and    computer readable instructions for further optimizing said polishing process by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing process.    
     
     
         47 . The computer readable medium of  claim 46 , wherein said one or more upstream wafer processing processes comprises at least one of an etch or dielectric deposition process.  
     
     
         48 . The computer readable medium of  claim 46 , wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.  
     
     
         49 . The computer readable medium of  claim 46 , wherein said one or more target parameters of said polishing process comprises a removal rate parameter.  
     
     
         50 . The computer readable medium of  claim 46 , wherein said one or more target parameters of said polishing process comprises a removal rate parameter and a bulk polish time.  
     
     
         51 . The computer readable medium of  claim 46 , said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.  
     
     
         52 . The computer readable medium of  claim 46 , said polishing wafer property information comprises copper clearing time, reflectance, thickness, and an electrical property.  
     
     
         53 . The computer readable medium of  claim 46 , wherein said polishing process comprises a bulk polish process, an endpoint process, and a barrier polish process.  
     
     
         54 . The computer readable medium of  claim 53 , wherein said polishing wafer property information comprises thickness profile information collected during or after said bulk polish process.  
     
     
         55 . The computer readable medium of  claim 53 , wherein said polishing wafer property information comprises copper clearing information collected during or after said endpoint process.  
     
     
         56 . The computer readable medium of  claim 53 , wherein said polishing wafer property information comprises an electrical property collected during or after said barrier polish process.  
     
     
         57 . The computer readable medium of  claim 44 , wherein said plating process comprises an electro chemical plating process and said polishing process comprises a chemical mechanical polishing process.