Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics

Abstract

A semiconductor memory device has 2 n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2 m (n>m) word lines among the 2 n word lines, and a second unit for not selecting a block of 2 k (m>k) word lines among the 2 m word lines. The second unit does not select the block of 2 k word lines, and selects a block of 2 k word lines prepared outside the 2 n word lines when any one of the 2 k word lines among the 2 m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

1 . A semiconductor memory device comprising: 
 2 n  word lines;    a plurality of bit lines;    a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;    a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines;    a sense amplifier for reading data out of said memory cells;    a first means for simultaneously selecting a block of 2 m  (n>m) word lines among said 2 n  word lines; and    a second means for not selecting a block of 2 k  (m>k) word lines among said 2 m  word lines, said second means not selecting said block of 2 k  word lines and selecting a block of 2 k  word lines prepared outside said 2 n  word lines when any one of said 2 k  word lines among said 2 m  word lines is defective.    
     
     
         2 . A semiconductor memory device as claimed in  claim 1 , wherein said selected word lines receive a negative voltage, and said unselected word lines receive a zero or positive voltage.  
     
     
         3 . A semiconductor memory device as claimed in  claim 1 , wherein said block of 2 n  word lines forms a real cell block, said block of 2 m  word lines forms an erase block, and said block of 2 k  word lines outside said block of 2 n  word lines forms a redundant cell block.  
     
     
         4 . A semiconductor memory device as claimed in  claim 1 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         5 . A semiconductor memory device comprising: 
 2 n  word lines;    a plurality of bit lines;    a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;    a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines;    a sense amplifier for reading data out of said memory cells;    a first means for simultaneously selecting a block of 2 m  (n>m) word lines among said 2 n  word lines; and    a second means for not selecting a block of 2 k  (m>k) word lines among said 2 m  word lines, data being written to any memory cell transistor, which is contained in said 2 k  word lines and whose threshold voltage is lower than the potential of an unselected word line, so that the threshold voltage of said memory cell transistor exceeds the potential of said unselected word line, and a block of 2 k  word lines prepared outside said 2 n  word lines being used as redundant word lines.    
     
     
         6 . A semiconductor memory device as claimed in  claim 5 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         7 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;    a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines; and    a sense amplifier for reading data out of said memory cells, wherein each word line is controlled such that a drain current of a memory cell transistor connected to said word line is lower than a channel current thereof, when writing data to said cell transistor to increase the threshold voltage of said memory cell transistor to be higher than the potential of an unselected word line.    
     
     
         8 . A semiconductor memory device as claimed in  claim 7 , wherein each word line is controlled by applying a signal in accordance with a pulse signal.  
     
     
         9 . A semiconductor memory device as claimed in  claim 7 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         10 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable;    a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines; and    a sense amplifier for reading data out of said memory cells, wherein an output current of said sense amplifier is changed according to a combination of ON states of two load transistors having different capacities, to realize a normal data read operation, an erase verify operation, and a write verify operation.    
     
     
         11 . A semiconductor memory device as claimed in  claim 10 , wherein a reference voltage is increased to provide a word line with a voltage, which is used to carry out said write verify or erase verify operations on any cell transistor connected to said word line.  
     
     
         12 . A semiconductor memory device as claimed in  claim 10 , wherein p-channel type and n-channel type transistors fabricated in the same process are connected in series like diodes to provide a word line with a voltage which is used to carry out said write verify or erase verify operations on any cell transistor connected to said word line.  
     
     
         13 . A semiconductor memory device as claimed in  claim 10 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         14 . A semiconductor memory device comprising: 
 a plurality of real memory cells divided into blocks;    a plurality of redundant memory cells to be replaced with defective ones of said real memory cells;    a plurality of defective address specifying means for specifying defective addresses of the respective blocks of said real memory cells; and    an address comparing means shared by said defective address specifying means, for comparing said defective addresses with addresses in said blocks of said real memory cells.    
     
     
         15 . A semiconductor memory device as claimed in  claim 14 , wherein said semiconductor memory device comprises: 
 a redundant circuit having said defective address specifying means and said address comparing means;    a real cell selecting means for receiving an output of said redundant circuit and a block address for specifying one of said real cell blocks, and controlling the selection and non-selection of said memory cells in said specified real cell block; and    a redundant cell selecting means for receiving the output of said redundant circuit and said block address, and controlling the selection and nonselection of said redundant cells.    
     
     
         16 . A semiconductor memory device comprising: 
 a real cell array having a plurality of memory cells, and a plurality of redundant cells to be replaced with defective memory cells of said real cell array;    a redundant information storing cell array for writing data to a defective address according to an externally provided address;    a cell selection circuit for selecting said redundant information storing cell array according to the externally provided address; and    a read circuit for reading an output of said redundant information storing cell array selected by said cell selection circuit, and providing a redundancy signal.    
     
     
         17 . A semiconductor memory device as claimed in  claim 16 , wherein said redundant information storing cell array and said read circuit are provided in plural, outputs of said read circuits are operated, and thereby a plurality of redundancy signals are output.  
     
     
         18 . A semiconductor memory device as claimed in  claim 16 , wherein said redundant information storing cell array is constituted by a plurality of nonvolatile memory cell transistors.  
     
     
         19 . A semiconductor memory device comprising electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device, wherein the allowable value of write or erase operations is carried out according to said internal algorithm being variable.  
     
     
         20 . A semiconductor memory device as claimed in  claim 19 , wherein said semiconductor memory device is constituted by a flash memory, and the allowable value of write or erase operations is determined by the number of write pulses or erase pulses.  
     
     
         21 . A semiconductor memory device as claimed in  claim 20 , wherein the maximum number of said pulses to be applied in a delivery test is reduced to impose severer conditions on said delivery test.  
     
     
         22 . A semiconductor memory device as claimed in  claim 19 , wherein said semiconductor memory device is constituted by a flash memory, and the allowable value of write or erase operations is determined by the width of write pulses or erase pulses.  
     
     
         23 . A semiconductor memory device as claimed in  claim 22 , wherein the maximum width of said pulses to be applied in a delivery test is reduced to impose severer conditions on said delivery test.  
     
     
         24 . A semiconductor memory device as claimed in  claim 19 , wherein a change of the allowable value of write or erase operations is carried out by applying a high voltage to a specific terminal of said semiconductor memory device.  
     
     
         25 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; and    a write voltage supply transistor for supplying a write voltage to a drain of said memory cell, wherein said write voltage supply transistor is formed of a p-channel type MIS transistor, which effectively applies the write voltage to the drain of said memory cell.    
     
     
         26 . A semiconductor memory device as claimed in  claim 25 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         27 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; and    a write voltage supply transistor for supplying a write voltage to a drain of said memory cell, wherein said write voltage supply transistor is formed of an n-channel type MIS transistor, and said semiconductor memory device comprises a step-up means being disposed to increase a gate voltage of said write voltage supply transistor at least up to a sum of the write voltage and a threshold voltage of said write voltage supply transistor.    
     
     
         28 . A semiconductor memory device as claimed in  claim 27 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         29 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of said MIS transistors being simultaneously discharged to collectively erase said memory cells;    a first power source for applying a normal selection voltage to a selected word line to select memory cells connected to said word line, when reading data; and    a second power source for establishing an unselected state on unselected word lines including memory cells that have been overerased by said collective erasing, when reading data.    
     
     
         30 . A semiconductor memory device as claimed in  claim 29 , wherein said memory cells are formed of enhancement n-channel type MIS transistors, said first power source is a positive voltage source for generating a normal positive voltage, and said second power source is a negative voltage source for generating a predetermined negative voltage for cutting OFF said overerased n-channel type MIS transistors that function as depletion transistors due to said overerasing.  
     
     
         31 . A semiconductor memory device as claimed in  claim 29 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         32 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of said MIS transistors being simultaneously discharged to collectively erase said memory cells;    a first row decoder for applying a normal voltage to a selected word line to select memory cells connected to said word line, when reading data; and    a second row decoder for applying a predetermined source voltage to the source of each memory cell connected to said selected word line, and applying an unselected state establishing voltage to the sources of memory cells, including those overerased by said collective erasing, connected to unselected word lines, when reading data.    
     
     
         33 . A semiconductor memory device as claimed in  claim 32 , wherein said memory cells are formed of enhancement n-channel type MIS transistors, and said second row decoder applies a low source voltage to the source of each cell transistor connected to said selected word line, and applies a voltage higher than the level of a selected bit line to the sources of memory cells connected to said unselected word lines.  
     
     
         34 . A semiconductor memory device as claimed in  claim 33 , wherein said second row decoder applies a voltage equal to the level of said selected bit line to the sources of memory cells connected to said unselected word lines, when reading data.  
     
     
         35 . A semiconductor memory device as claimed in  claim 32 , wherein said semiconductor memory device is constituted by a flash memory.  
     
     
         36 . A semiconductor memory device comprising; 
 a plurality of word lines;    a plurality of bit lines;    a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of said MIS transistors being simultaneously discharged to collectively erase said memory cells, wherein a method of saving overerased memory cells of said semiconductor memory device detects memory cells that have been overerased by said collective erasing, and writing data to said overerased memory cells, thereby saving said overerased memory cells.    
     
     
         37 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof;    a write-before-erase means for writing all memory cells of said memory cell array before erasing them;    an erase means for erasing all of said written memory cells by said write-before-erase means and for verifying said erasing;    an overerased cell detecting means for detecting overerased memory cells among said erased and verified memory cells by said erase means; and    an overerased cell saving means for writing said overerased memory cells detected by said overerased cell detecting means, thereby saving said overerased memory cells.    
     
     
         38 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines; and    a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable, wherein said nonvolatile memory cells are divided into a plurality of cell blocks to be selected according to a block selection signal provided by a block address buffer, each of said cell blocks has a data erasing means and a latching means for latching said block selection signal, and thereby data of said cell blocks that have latched said block selection signal are simultaneously erased.    
     
     
         39 . A semiconductor memory device as claimed in  claim 38 , wherein said semiconductor memory device comprises data decision circuits for discriminating cell data in said respective cell blocks, expected value storage circuits each for storing an expected value for write and write-verify operations as well as an expected value for an erase-verify operation, coincidence circuits each for comparing an output signal of said data decision circuit with the expected value and providing a coincidence signal, and a logic circuit for providing a logical multiply of the coincidence signals from said respective cell blocks.  
     
     
         40 . A semiconductor memory device as claimed in  claim 38 , wherein said semiconductor memory device comprises data decision circuits for discriminating cell data in said respective cell blocks, expected value generators each for generating an expected value for write and write-verify operations as well as an expected value for an erase-verify operation, coincidence circuits each for comparing an output signal of said data decision circuit with the expected value and providing a coincidence signal, and a logic circuit for providing a logical multiply of the coincidence signals from said respective cell blocks.  
     
     
         41 . A semiconductor memory device as claimed in  claim 38 , wherein said semiconductor memory device comprises data decision circuits for discriminating cell data in said respective cell blocks, data inversion circuits each for inverting an output signal of said data decision circuit in accordance with erase and write operations, and a logic circuit for providing a logical multiply of said data inversion circuits from said respective cell blocks.  
     
     
         42 . A semiconductor memory device comprising: 
 a first terminal for receiving a normal voltage;    a second terminal for receiving a high voltage from a high-voltage supply means, and said high voltage being required to write or erase data and higher than said normal voltage required to read data; and    a third terminal for providing said high-voltage supply means with a control signal that controls the supply of said high voltage.    
     
     
         43 . A semiconductor memory device as claimed in  claim 42 , wherein said semiconductor memory device comprises a command determination means that determines whether or not an operation specified by an input command to said semiconductor memory device requires said high voltage, and provides a control signal to start the supply of said high voltage if the operation requires said high voltage, and if not, a control signal to stop said high voltage.  
     
     
         44 . A semiconductor memory device as claimed in  claim 42 , wherein said semiconductor memory device comprises a voltage test means that tests whether or not said supplied high voltage is greater than a predetermined value, said high voltage requiring operation being started if said supplied high voltage is greater than said predetermined value.  
     
     
         45 . A semiconductor memory device as claimed in  claim 42 , wherein said semiconductor memory device comprises a delay means that delays the start of said high voltage requiring operation by a predetermined time after said control signal to start the supply of said high voltage is sent.  
     
     
         46 . A semiconductor memory device as claimed in  claim 42 , wherein said semiconductor memory device is determined as a flash memory.  
     
     
         47 . A semiconductor memory device comprising: 
 a step-up circuit for supplying a high voltage that is required to write or erase data and higher than a normal voltage required to read data; and    a command determination means that determines whether or not an operation specified by an input command to said semiconductor memory device requires the high voltage, and provides a control signal to start the supply of said high voltage if the operation requires said high voltage, and if not, a control signal to stop said high voltage.    
     
     
         48 . A semiconductor memory device as claimed in  claim 47 , wherein a passive component of said step-up circuit is arranged on an outside of said semiconductor memory device.  
     
     
         49 . A semiconductor memory device as claimed in  claim 48 , wherein said passive component is an inductance element.  
     
     
         50 . A semiconductor memory device as claimed in  claim 48 , wherein said passive component is a capacitance element.  
     
     
         51 . A semiconductor memory device as claimed in  claim 47 , wherein said semiconductor memory device comprises a voltage test means that tests whether or not said supplied high voltage is greater than a predetermined value, said high voltage requiring operation being started if said supplied high voltage is greater than said predetermined value.  
     
     
         52 . A semiconductor memory device as claimed in  claim 47 , wherein said semiconductor memory device comprises a delay means that delays the start of said high voltage requiring operation by a predetermined time after said control signal to start the supply of said high voltage is sent.  
     
     
         53 . A semiconductor memory device as claimed in  claim 48 , wherein said semiconductor memory device and said passive component are sealed in the same package.  
     
     
         54 . A semiconductor memory device as claimed in  claim 47 , wherein said semiconductor memory device is determined as a flash memory.  
     
     
         55 . A computer system having a semiconductor memory device as a part of a storage means and a step-transistor up circuit for generating a high voltage required to write and erase data to and from said semiconductor memory device, wherein said computer system comprises: 
 a control means for automatically generating a control signal to control said step-up circuit, in response to an access operation to said semiconductor memory device.    
     
     
         56 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of memory cells disposed at each intersection of said word lines and said bit lines, and a decoder circuit for selecting said memory cell according to an address signal in a normal decoding function and for carrying out a full selection operation or a nonselection operation of said word lines or said bit lines in a test function; and    an output row or a decoding row connected to a first power source and a second power source, said first power source and a second power voltage, and said second power source supplying a reference voltage or said high voltage in response to a control signal.    
     
     
         57 . A semiconductor memory device as claimed in  claim 56 , wherein said semiconductor memory device comprises: 
 a first detector including a first transistor of first conduction type, a second transistor of second conduction type connected to said first transistor in series, a node between said first and second transistor in series, a node between said first and second transistors, forming a first output end of said first detector, a high voltage supply source connected to gates of said first and second transistors, an external input terminal connected to an end of said first transistor, and a low voltage supply source connected to an end of said second transistor;    a second detector including a third of second conduction type, a fourth transistor of first conduction type connected to said third transistor in series, a node between said third and fourth transistors, forming a second output end of said second detector, said high voltage supply source connected to gates of said third and fourth transistors, said external input terminal connected to an end of said third transistor, and said low voltage supply source connected to an end of said fourth transistor; and    an operation circuit carrying out a logical operation according to output signals from said first and second detectors, to provide a test signal to said decoder circuit.    
     
     
         58 . A semiconductor memory device as claimed in  claim 56 , wherein said semiconductor memory device is determined as a flash memory.  
     
     
         59 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of memory cells disposed at each intersection of said word lines and said bit lines;    a decoder circuit for selecting said memory cell according to an address signal in a normal decoding function and for carrying out a full selection operation or a nonselection operation of said word lines or said bit lines in a test function; and    an output row or a decoding row connected to a first power source and a second power source, said first power source supplying a reference voltage, and said second power source supplying a reference voltage or said high voltage in response to a control signal.    
     
     
         60 . A semiconductor memory device as claimed in  claim 59 , wherein said semiconductor memory device comprises: 
 a first detector including a first transistor of first conduction type, a second transistor of second conduction type connected to said first transistor in series, a node between said first and second transistors, forming a first output end of said first detector, a high voltage supply source connected to gates of said first and second transistors, an external input terminal connected to an end of said first transistor, and a low voltage supply source connected to an end of said second transistor;    a second detector including a third transistor of second conduction type, a fourth transistor of first conduction type connected to said third transistor in series, a node between said third and fourth transistors, forming a second output end of said second detector, said high voltage supply source connected to gates of said third and fourth transistors, said external input terminal connected to an end of said third transistor, and said low voltage supply source connected to an end of said fourth transistor; and    an operation circuit carrying out a logical operation according to output signals from said first and second detectors, to provide a test signal to said decoder circuit.    
     
     
         61 . A semiconductor memory device as claimed in  claim 59 , wherein said semiconductor memory device is determined as a flash memory.