High speed data bus

Abstract

The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

What is claimed is:  
     
         1 . A memory circuit comprising: 
 at least one electrical contact to receive digital data;    at least one synchronous-DRAM memory;    a state decoder for receiving a chip select signal targeted for the synchronous-DRAM memory; and    at least one switch having one or more inputs connected to corresponding ones of said one or more electrical contacts, whereby the synchronous-DRAM memory is selectively decoupled from a bus in response to a change in state in the chip select signal.    
     
     
         2 . A device comprising: 
 at least one electrical contact arranged to receive digital data;    a state decoder for receiving a chip select signal targeted for a memory circuit; and    at least one switch having one or more inputs connected to corresponding ones of said one or more electrical contacts, whereby the memory circuit is selectively decoupled from a bus in response to a change in state in the chip select signal.    
     
     
         3 . The device of  claim 2 , wherein said switch additionally comprises a control portion for selectively opening and closing said switch.  
     
     
         4 . The device of  claim 3 , wherein said control portion is coupled to the electrical contact.  
     
     
         5 . The device of  claim 4 , additionally comprising: a logic circuit having an input coupled to at least one of said electrical contacts, and having an output coupled to said control portion of said switch.  
     
     
         6 . The device of  claim 2 , wherein the memory circuit comprises SDRAM.  
     
     
         7 . A memory module comprising: 
 at least one electrical contact arranged to receive digital data; and    at least one switch having one or more inputs connected to corresponding ones of said one or more electrical contacts, and wherein activation of the switch is operated to control the parasitic capacitance of the bus.    
     
     
         8 . The memory module of  claim 7 , wherein said switch additionally comprises a control portion for selectively opening and closing said switch.  
     
     
         9 . The memory module of  claim 7 , wherein said control portion is coupled to an additional electrical contact on said printed circuit board.  
     
     
         10 . The memory module of  claim 7 , additionally comprising: 
 electrical contacts arranged on said printed circuit board for receiving memory access control signals; and    a logic circuit having an input coupled to at least one of said electrical contacts, and having an output coupled to said control portion of said switch.    
     
     
         11 . A memory circuit comprising: 
 at least one switch for decoupling the memory integrated circuit from the data bus, and wherein activation of the switch is operated to control the parasitic capacitance of the bus.    
     
     
         12 . The memory circuit of  claim 11 , wherein said switch additionally comprises a control portion for selectively opening and closing said switch.  
     
     
         13 . The memory circuit of  claim 12 , additionally comprising: 
 electrical contacts arranged for receiving memory access control signals; and    a logic circuit having an input coupled to at least one of said electrical contacts, and having an output coupled to said control portion of said switch.    
     
     
         14 . A circuit comprising: 
 at least one electrical contact arranged to receive digital data;    a memory;    a memory controller comprising an address bit decoder configured to selectively enable one or more memory controller outputs in response to received address bits; and    at least one switch in a data bus that is resides at least in part in the memory circuit, wherein the switch, the memory, and the memory controller each collectively reside within a single integrated circuit, and wherein activation of the switch is operated to control the parasitic capacitance of the bus.    
     
     
         15 . The circuit of  claim 14 , wherein said switch additionally comprises a control portion for selectively opening and closing said switch.  
     
     
         16 . The circuit of  claim 15 , wherein said control portion is coupled to an additional electrical contact.  
     
     
         17 . The memory module of  claim 16 , additionally comprising: 
 electrical contacts arranged for receiving memory access control signals; and    a logic circuit having an input coupled to at least one of said electrical contacts, and having an output coupled to said control portion of said switch.    
     
     
         18 . A device comprising: 
 a bus;    a memory; and    at least one switch that selectively decouples the memory from the bus in response to a change in state in a chip select signal.    
     
     
         19 . The device of  claim 18 , wherein the memory comprises SDRAM.  
     
     
         20 . The device of  claim 18 , wherein said switch additionally comprises a control portion for selectively opening and closing said switch.  
     
     
         21 . The device of  claim 18 , additionally comprising: a logic circuit having an input coupled to the bus and having an output coupled to the switch.  
     
     
         22 . The device of  claim 18 , wherein the memory circuit comprises SDRAM.