Negative voltage generator for a semiconductor memory device

Abstract

A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

1 . A negative voltage level detector for a semiconductor device comprising: 
 a differential amplifier having a first input and a second input;    a first voltage divider coupled to the first input of the differential amplifier; and    a second voltage divider coupled to the second input of the differential amplifier, and adapted to drive the second input of the differential amplifier responsive to a negative voltage.    
     
     
         2 . A negative voltage level detector according to  claim 1  wherein the first voltage divider is adapted to drive the first input of the differential amplifier responsive to a reference voltage.  
     
     
         3 . A negative voltage level detector according to  claim 2  wherein the first voltage divider comprises: 
 a first resistor coupled between the reference voltage and the first input of the differential amplifier; and  
 a second resistor coupled between the first input of the differential amplifier and a power supply terminal.  
 
     
     
         4 . A negative voltage level detector according to  claim 2  wherein the second voltage divider comprises: 
 a first resistor coupled between a reference voltage and the second input of the differential amplifier; and  
 a second resistor coupled between the second input of the differential amplifier and the negative voltage.  
 
     
     
         5 . A negative voltage level detector according to  claim 1  further comprising an inverter having an input coupled to an output of the differential amplifier.  
     
     
         6 . A negative voltage level detector according to  claim 1:   wherein the first voltage divider comprises: 
 a first resistor coupled between a reference voltage and the first input of the differential amplifier, and  
 a second resistor coupled between the first input of the differential amplifier and a power supply terminal;  
   wherein the second voltage divider comprises: 
 a third resistor coupled between the reference voltage and the second input of the differential amplifier, and  
 a fourth resistor coupled between the second input of the differential amplifier and the negative voltage;  
   wherein the differential amplifier comprises: 
 a differential pair of input transistors coupled to the first and second input terminals,  
 a current source coupled to the differential pair of transistors, and  
 a load coupled to the differential pair of transistors; and  
   further comprising an inverter having an input coupled to an output of the differential amplifier.    
     
     
         7 . A negative voltage level detector according to  claim 1  wherein the differential amplifier comprises a current mirror load coupled to a power supply terminal.  
     
     
         8 . A negative voltage level detector according to  claim 1  wherein: 
 the semiconductor device is a memory device utilizing a negative word line scheme; and  
 the negative voltage is a negative voltage source for negatively biasing a word line.  
 
     
     
         9 . A negative voltage level detector for a semiconductor device comprising: 
 means for dividing a reference voltage, thereby generating a first divided signal;    means for dividing a negative voltage, thereby generating a second divided signal; and    means for amplifying the difference between the first and second divided signals.    
     
     
         10 . A negative voltage level detector according to  claim 9  wherein the means for dividing a reference voltage comprises: 
 a first resistor coupled between the reference voltage and a first input of the means for amplifying; and  
 a second resistor coupled between the first input of the means for amplifying and a power supply terminal.  
 
     
     
         11 . A negative voltage level detector according to  claim 9  wherein the means for dividing a negative voltage comprises: 
 a first resistor coupled between a reference voltage and a second input of the means for amplifying; and  
 a second resistor coupled between the second input of the means for amplifying and the negative voltage.  
 
     
     
         12 . A negative voltage level detector according to  claim 9  wherein the means for amplifying comprises a differential amplifier referenced to a power supply voltage.  
     
     
         13 . A negative voltage level detector according to  claim 9  wherein: 
 the semiconductor device is a memory device utilizing a negative word line scheme; and  
 the negative voltage is a negative voltage for biasing a word line.  
 
     
     
         14 . A negative voltage level detector for a semiconductor device comprising: 
 a differential amplifier having a first input and a second input;    a first voltage divider coupled to the first input of the differential amplifier and adapted to drive the first input of the differential amplifier responsive to a reference voltage, wherein the first voltage divider is adapted to maintain the first input of the differential amplifier at a positive voltage; and    a second voltage divider coupled to the second input of the differential amplifier and adapted to drive the second input of the differential amplifier responsive to a negative voltage, wherein the second voltage divider is adapted to maintain the second input of the differential amplifier at a positive voltage.    
     
     
         15 . A negative voltage level detector according to  claim 14  wherein the first voltage divider comprises: 
 a first resistor coupled between the reference voltage and the first input of the differential amplifier; and  
 a second resistor coupled between the first input of the differential amplifier and a power supply terminal.  
 
     
     
         16 . A negative voltage level detector according to  claim 14  wherein the second voltage divider comprises: 
 a first resistor coupled between a reference voltage and the second input of the differential amplifier; and  
 a second resistor coupled between the second input of the differential amplifier and the negative voltage.  
 
     
     
         17 . A method for detecting a negative voltage in a semiconductor device comprising: 
 dividing a reference-voltage, thereby generating a first divided signal;    dividing the negative voltage, thereby generating a second divided signal; and    amplifying the difference between the first and second divided signals.    
     
     
         18 . A method according to  claim 17  wherein dividing the reference voltage comprises level shifting the reference voltage.  
     
     
         19 . A method according to  claim 17  wherein dividing the negative voltage comprises level shifting the negative voltage.  
     
     
         20 . A method according to  claim 17  wherein amplifying the difference between the first and second divided signals comprises referencing a differential amplifier to a power supply voltage.  
     
     
         21 . A method according to  claim 17  wherein: 
 the semiconductor device is a memory device utilizing a negative word line scheme; and  
 the negative voltage is a negative voltage for biasing a word line.  
 
     
     
         22 . A negative voltage regulator for a semiconductor device comprising: 
 a differential amplifier having a first input, a second input, and an output;    an output transistor coupled to the output of the differential amplifier and arranged to generate a second negative voltage from a first negative voltage;    a first voltage divider coupled to the first input of the differential amplifier; and    a second voltage divider coupled to the second input of the differential amplifier, and adapted to drive the second input of the differential amplifier responsive to the second negative voltage.    
     
     
         23 . A negative voltage regulator according to  claim 22  wherein the first voltage divider is adapted to drive the first input of the differential amplifier responsive to a reference voltage.  
     
     
         24 . A negative voltage regulator according to  claim 23  wherein the first voltage divider comprises: 
 a first resistor coupled between the reference voltage and the first input of the differential amplifier; and  
 a second resistor coupled between the first input of the differential amplifier and a power supply terminal.  
 
     
     
         25 . A negative voltage regulator according to  claim 22  wherein the second voltage divider comprises: 
 a first resistor coupled between a reference voltage and the second input of the differential amplifier; and  
 a second resistor coupled between the second input of the differential amplifier and the second negative voltage.  
 
     
     
         26 . A negative voltage regulator according to  claim 32:   wherein the first voltage divider comprises: 
 a first resistor coupled between a reference voltage and the first input of the differential amplifier, and  
 a second resistor coupled between the first input of the differential amplifier and a power supply terminal;  
   wherein the second voltage divider comprises: 
 a third resistor coupled between the reference voltage and the second input of the differential amplifier, and  
 a fourth resistor coupled between the second input of the differential amplifier and a the second negative voltage;  
   wherein the differential amplifier comprises: 
 a differential pair of input transistors coupled to the first and second input terminals,  
 a current source coupled to the differential pair of transistors, and  
 a load coupled to the differential pair of transistors; and  
   wherein the output transistor has a second terminal coupled to an output terminal of the differential amplifier.    
     
     
         27 . A negative voltage regulator according to  claim 22  wherein: 
 the semiconductor device is a memory device utilizing a negative word line scheme; and  
 the second negative voltage is a negative voltage source for negatively biasing a word line.  
 
     
     
         28 . A negative voltage regulator for a semiconductor device comprising: 
 means for generating a second negative voltage from a first negative voltage responsive to a drive signal;    means for dividing a reference voltage, thereby generating a first divided signal;    means for dividing the second negative voltage, thereby generating a second divided signal;    means for amplifying the difference between the first and second divided signals, thereby generating the drive signal.    
     
     
         29 . A negative voltage regulator according to  claim 28  wherein the means for dividing the reference voltage comprises: 
 a first resistor coupled between the reference voltage and a first input of the means for amplifying; and  
 a second resistor coupled between the first input of the means for amplifying and a power supply terminal.  
 
     
     
         30 . A negative voltage regulator according to  claim 28  wherein the means for dividing the second negative voltage comprises: 
 a first resistor coupled between a reference voltage and the second input of the means for amplifying; and  
 a second resistor coupled between the second input of the means for amplifying and the second negative voltage.  
 
     
     
         31 . A negative voltage regulator according to  claim 28  wherein: 
 the semiconductor device is a memory device utilizing a negative word line scheme; and  
 the first negative voltage is a negative voltage for biasing a word line.  
 
     
     
         32 . A negative voltage regulator for a semiconductor device comprising: 
 a differential amplifier having a first input, a second input, and an output;    an output transistor coupled to the output of the differential amplifier and arranged to generate a second negative voltage from a first negative voltage;    a first voltage divider coupled to the first input of the differential amplifier and adapted to drive the first input of the differential amplifier responsive to a reference voltage, wherein the first voltage divider is adapted to maintain the first input of the differential amplifier at a positive voltage; and    a second voltage divider coupled to the second input of the differential amplifier and adapted to drive the second input of the differential amplifier responsive to the second negative voltage, wherein the second voltage divider is adapted to maintain the second input of the differential amplifier at a positive voltage.    
     
     
         33 . A negative voltage level detector according to  claim 32  wherein the first voltage divider comprises: 
 a first resistor coupled between the reference voltage and the first input of the differential amplifier; and  
 a second resistor coupled between the first input of the differential amplifier and a power supply terminal.  
 
     
     
         34 . A negative voltage level detector according to  claim 32  wherein the second voltage divider comprises: 
 a first resistor coupled between a reference voltage and the second input of the differential amplifier; and  
 a second resistor coupled between the second input of the differential amplifier and the second negative voltage.  
 
     
     
         35 . A method for generating a first negative voltage in a semiconductor device comprising: 
 generating a second negative voltage;    dividing a reference voltage, thereby generating a first divided signal;    dividing the first negative voltage, thereby generating a second divided signal;    amplifying the difference between the first and second divided signals, thereby generating a drive signal; and    driving an output transistor coupled between the first negative voltage and the second negative voltage responsive to the drive signal.    
     
     
         36 . A method according to  claim 35  wherein dividing the reference voltage comprises level shifting the reference voltage.  
     
     
         37 . A method according to  claim 35  wherein dividing the first negative voltage comprises level shifting the first negative voltage.  
     
     
         38 . A method according to  claim 35  wherein amplifying the difference between the first and second divided signals comprises referencing a differential amplifier to the second negative voltage.  
     
     
         39 . A method according to  claim 35  wherein: 
 the semiconductor device is a memory device utilizing a negative word line scheme; and  
 the first negative voltage is a negative voltage for biasing a word line.