Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and agate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer;    a channel region formed between the first and second impurity diffusion layers;    a gate insulation layer formed at least on the channel region; and    a gate electrode formed on the gate insulation layer,    wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer.    
     
     
         2 . The semiconductor device according to  claim 1 , 
 wherein a nitrogen/tantalum ratio (x) shown by TaN x  in the tantalum nitride layer is 0.25 to 1.0.    
     
     
         3 . The semiconductor device according to  claim 2 , 
 wherein the nitrogen/tantalum ratio (x) shown by TaN x  in the tantalum nitride layer is about 0.5.    
     
     
         4 . The semiconductor device according to  claim 1 , 
 wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.    
     
     
         5 . The semiconductor device according to  claim 1 , 
 wherein the gate electrode is formed of the tantalum nitride layer.    
     
     
         6 . The semiconductor device according to  claim 1 , 
 wherein the gate electrode has a multilayer structure comprising the tantalum nitride layer and a metal layer.    
     
     
         7 . The semiconductor device according to  claim 6 , 
 wherein the gate electrode comprises a cap layer formed in the uppermost layer.    
     
     
         8 . The semiconductor device according to  claim 7 , 
 wherein the cap layer is formed of at least one material selected from TaN x , TaSi x N y , TiN x , TiAl x N y , Si, and silicide of a transition metal.    
     
     
         9 . The semiconductor device according to  claim 1 , 
 wherein silicide layers are formed in part of the first and second impurity diffusion layers.    
     
     
         10 . The semiconductor device according to  claim 1 , 
 wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure, or is a silicon layer containing impurities at a concentration of 10 17  cm −3  or less and having a thickness one-third a gate length or less, which is formed on a bulk semiconductor substrate containing impurities at a concentration of more than 10 17  cm −3 .    
     
     
         11 . A complementary semiconductor device comprising an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, 
 wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor includes: 
 first and second impurity diffusion layers for forming a source region and a drain region which are formed in a semiconductor layer;  
 a channel region formed between the first and second impurity diffusion layers;  
 a gate insulation layer formed on the channel region; and  
 a gate electrode formed on the gate insulation layer, and  
 wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer.  
   
     
     
         12 . The complementary semiconductor device according to  claim 11 , 
 wherein a nitrogen/tantalum ratio (x) shown by TaN in the tantalum nitride layer is 0.25 to 1.0.    
     
     
         13 . The complementary semiconductor device according to  claim 12 , 
 wherein the nitrogen/tantalum ratio (x) shown by TaN x  in the tantalum nitride layer is about 0.5.    
     
     
         14 . The complementary semiconductor device according to  claim 11 , 
 wherein the tantalum nitride-layer has a thickness of 1 nm to 300 nm.    
     
     
         15 . The complementary semiconductor device according to  claim 11 , 
 wherein the gate electrode is formed of the tantalum nitride layer.    
     
     
         16 . The complementary semiconductor device according to  claim 11 , 
 wherein the gate electrode has a multilayer structure comprising the tantalum nitride layer and a metal layer.    
     
     
         17 . The complementary semiconductor device according to  claim 16 , 
 wherein the gate electrode comprises a cap layer formed in the uppermost layer.    
     
     
         18 . The complementary semiconductor device according to  claim 17 , 
 wherein the cap layer is formed of at least one material selected from TaN x , TaSi x N y , TiN x , TiAl x N y , Si, and silicide of a transition metal.    
     
     
         19 . The complementary semiconductor device according to  claim 11 , 
 wherein silicide layers are formed in part of the first and second impurity diffusion layers.    
     
     
         20 . The complementary semiconductor device according to  claim 11 , 
 wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure, or is a silicon layer containing impurities at a concentration of 10 17  cm 3  or less and having a thickness one-third a gate length or less, which is formed on a bulk semiconductor substrate containing impurities at a concentration of more than 10 17  cm 3 .    
     
     
         21 . A method of manufacturing a semiconductor device comprising the following steps (a) to (c): 
 (a) a step of forming a gate insulation layer on a semiconductor layer;    (b) a step of forming a gate electrode on the gate insulation layer, and forming a tantalum nitride layer in a region in contact with at least the gate insulation layer; and    (c) a step of forming first and second impurity diffusion layers forming a source region and a drain region by introducing impurities into the semiconductor layer.    
     
     
         22 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein the tantalum nitride layer is formed so that the nitrogen/tantalum ratio (x) shown by TaN x  is 0.25 to 1.0.    
     
     
         23 . The method of manufacturing a semiconductor device according to  claim 22 , 
 wherein the nitrogen/tantalum ratio (x) shown by TaN x  in the tantalum nitride layer is about 0.5.    
     
     
         24 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.    
     
     
         25 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein the gate electrode is formed of the tantalum nitride layer.    
     
     
         26 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein the gate electrode has a multilayer structure comprising the tantalum nitride layer and a metal layer.    
     
     
         27 . The method of manufacturing a semiconductor device according to  claim 26 , 
 wherein the gate electrode comprises a cap layer formed in the uppermost layer.    
     
     
         28 . The method of manufacturing a semiconductor device according to  claim 27 , 
 wherein the cap layer is formed of at least one material selected from TaN x , TaSi x N y , TiN x , TiAl x N y , Si, and silicide of a transition metal.    
     
     
         29 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein silicide layers are formed in part of the first and second impurity diffusion layers.    
     
     
         30 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure , or is a silicon layer containing impurities at a concentration of 10 17  cm −3  or less and having a thickness one-third a gate length or less, which is formed on a bulk semiconductor substrate containing impurities at a concentration of more than 10 17  cm −3 .    
     
     
         31 . The method of manufacturing a semiconductor device according to  claim 21 , 
 wherein the first and second impurity diffusion layers are formed in a self-alignment manner using the gate electrode as a mask in the step (c).    
     
     
         32 . The method of manufacturing a semiconductor device according to  claim 21 , further comprising a step (e) of forming a side-wall spacer on a side of the gate electrode after the step (c).  
     
     
         33 . The method of manufacturing a semiconductor device according to  claim 32 , 
 wherein silicide layers are formed on exposed areas of the first and second impurity diffusion layers after the step (e).    
     
     
         34 . A method of manufacturing a complementary semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the method comprising the following steps (a) to (c): 
 (a) a step of forming a gate insulation layer on a semiconductor layer;    (b) a step of forming a gate electrode on the gate insulation layer, and forming a tantalum nitride layer in a region in contact with at least the gate insulation layer; and    (c) a step of introducing impurities into the semiconductor layer to form a source region and a drain region, comprising forming N-type first and second impurity diffusion layers for the N-channel insulated gate field effect transistor and forming P-type first and second impurity diffusion layers for the P-channel insulated gate field effect transistor.    
     
     
         35 . The method of manufacturing a complementary semiconductor device according to  claim 34 , 
 wherein the tantalum nitride layer is formed so that the nitrogen/tantalum ratio (x) shown by TaN x  is 0.25 to 1.0.    
     
     
         36 . The method of manufacturing a complementary semiconductor device according to  claim 35 , 
 wherein the nitrogen/tantalum ratio (x) shown by TaN x  in the tantalum nitride layer is about 0.5.    
     
     
         37 . The method of manufacturing a complementary semiconductor device according to  claim 34 , 
 wherein the tantalum nitride layer has a thickness of 1 nm to 300 nm.    
     
     
         38 . The method of manufacturing a complementary semiconductor device according to  claim 34 , 
 wherein the gate electrode is formed of the tantalum nitride layer.    
     
     
         39 . The method of manufacturing a complementary semiconductor device according to  claim 34 , 
 wherein the gate electrode has a multilayer structure comprising the tantalum nitride layer and a metal layer.    
     
     
         40 . The method of manufacturing a complementary semiconductor device according to  claim 39 , 
 wherein the gate electrode comprises a cap layer formed in the uppermost layer.    
     
     
         41 . The method of manufacturing a complementary semiconductor device according to  claim 40 , 
 wherein the cap layer is formed of at least one material selected from TaN x , TaSi x N y , TiN x , TiAl x N y , Si, and silicide of a transition metal.    
     
     
         42 . The method of manufacturing a complementary semiconductor device according to  claim 34 , 
 wherein the semiconductor layer has a silicon on insulator (SOI) structure or a silicon on nothing (SON) structure, or is a silicon layer containing impurities at a concentration of 10 17  cm −3  or less and having a thickness one-third a gate length or less, which is formed on a bulk semiconductor substrate containing impurities at a concentration of more than 10 17  cm 3 .    
     
     
         43 . The method of manufacturing a complementary semiconductor device according to  claim 34 , 
 wherein the first and second impurity diffusion layers are formed by self-alignment using the gate electrode as a mask in the step (c).    
     
     
         44 . The method of manufacturing a complementary semiconductor device according to  claim 34 , further comprising a step (e) of forming a side-wall spacer on a side of the gate electrode after the step (c).  
     
     
         45 . The method of manufacturing a complementary semiconductor device according to  claim 44 , 
 wherein silicide layers are formed on exposed areas of the first and second impurity diffusion layers after the step (e).