System and method for translation buffer accommodating multiple page sizes

Abstract

A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays identifies a corresponding physical page address and the other array identifies a corresponding variable page address that in comparison to a variable portion of the virtual address, will indicate whether the entry in the first array has a matching entry. If the first array identifies a matching physical page address, then the physical page address is combined with the offset of the virtual address to yield a physical address translation of the virtual address.

What is claimed is:  
     
         1 . An apparatus, comprising: 
 a translation buffer to store a portion of a physical page address associated with a physical memory; and    a page size bias input coupled to the translation buffer to indicate a plurality of positions within a lower portion of a tag of a virtual address, the plurality of positions corresponding to a plurality of page sizes within the physical memory.    
     
     
         2 . The apparatus of  claim 1 , further comprising: 
 a variable page address input coupled to the translation buffer.    
     
     
         3 . The apparatus of  claim 1 , further comprising: 
 a decoder to couple the page size bias input to the translation buffer.    
     
     
         4 . The apparatus of  claim 1 , wherein the page size bias input is to map a range of positions spanning a smallest page size to a largest page size of the plurality of page sizes.  
     
     
         5 . An apparatus, comprising: 
 a physical memory having a plurality of page sizes; and    a translation buffer having a page size bias input to indicate a plurality of positions within a lower portion of a tag of a virtual address, the plurality of positions corresponding to the plurality of page sizes within the physical memory.    
     
     
         6 . The apparatus of  claim 1 , further comprising: 
 a variable page address input coupled to the translation buffer.    
     
     
         7 . The apparatus of  claim 6 , further comprising: 
 a decoder coupled to the page size bias input and the variable page address input, wherein the decoder is to provide a first wordline to a first wordline select output included in the decoder.    
     
     
         8 . The apparatus of  claim 7 , further comprising: 
 a physical memory page address output coupled to the translation buffer; and    a first array coupled to the variable page address input and the first wordline select output, wherein the first array is to store a corresponding physical memory page address to be provided to the physical memory page address output, and a virtual fixed page address to be provided to a virtual fixed page address output.    
     
     
         9 . The apparatus of  claim 8  wherein the first array is a direct-mapped array to store the virtual fixed page address, a page mask, and the corresponding physical memory page address.  
     
     
         10 . The apparatus of  claim 7 , further comprising: 
 a direct-mapped array coupled to the variable page address input and the first wordline select output, the direct-mapped array to store an entry including a virtual address tag, a flag indicating validity of the entry, and a page mask, wherein the direct-mapped array is to provide an indication of a translation lookaside buffer miss or a translation lookaside buffer hit.    
     
     
         11 . The apparatus of  claim 10 , further comprising: 
 a virtual fixed page address input coupled to the translation buffer; and    a content addressable array coupled to the virtual fixed page address input, the content addressable array having a third wordline select output coupled to the direct-mapped array, wherein the content addressable array is to store bits to select the entry for invalidation.    
     
     
         12 . A system comprising: 
 a processor coupled to a physical memory having a plurality of page sizes;    a translation buffer to store a portion of a physical page address associated with the physical memory; and    a page size bias input coupled to the translation buffer to indicate a plurality of positions within a lower portion of a tag of a virtual address, the plurality of positions corresponding to the plurality of page sizes.    
     
     
         13 . The system of  claim 12 , further comprising: 
 a second processor coupled to the physical memory.    
     
     
         14 . The system of  claim 12 , further comprising: 
 a page table coupled to the translation buffer.    
     
     
         15 . The system of  claim 12 , further comprising: 
 a decoder coupled to the page size bias input, wherein the decoder is to provide a first wordline to a first wordline select output included in the decoder.