Data cache system

Abstract

An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.

We claim:  
     
         1 . A data cache system in a multimedia processor, having a plurality of modules including a processor, a main memory, a data cache and a plurality of I/O devices, wherein, 
 said data cache is configured in an N-way set associative structure, and is capable of adding information indicating which way of said data cache is switchable, as an option of read and write command used for accessing the data cache via an internal memory bus.    
     
     
         2 . A data cache system in a multimedia processor, having a plurality of modules including a processor, a main memory, a data cache and a plurality of I/O devices, wherein 
 said data cache and a data streamer are connected to a first internal memory bus, and further, 
 said data streamer and said main memory are connected to a second internal memory bus, allowing a data traffic to be distributed.