Semiconductor integrated circuit

Abstract

It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

1 . A semiconductor integrated circuit including a cache capability provided by a Translation Look-aside Buffer (TLB) and a cache, wherein 
 said cache comprises a cache memory index (TAG) memory module and a cache data memory module, said cache data memory module being divided into first and second cache data memory modules which are disposed on both sides of said TAG memory module; and    input/output circuits of said TLB are opposed to an input/output circuit of said TAG memory module and input/output circuits of said first and second cache data memory modules across a bus area.    
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , wherein 
 each of said TAG memory module and said first and second cache data memory modules is further divided into two and said divided modules are disposed on both sides of the TLB.    
     
     
         3 . A semiconductor integrated circuit including a cache capability provided by a translation look-aside buffer (TLB) and a cache, wherein 
 said TLB comprises a TLB TAG module storing address change data and a TLB data memory module storing Translation Look-aside data;    said cache comprises a TAG memory module storing cache memory index data and a cache data memory module storing cache data;    said TAG memory module is divided into a plurality of modules and said cache data memory module is divided into a plurality of modules;    said divided TAG memory modules are disposed on both sides of a longitudinal arrangement direction of the TLB TAG module and the TLB data memory module with the TLB TAG module and the TLB data memory module being sandwiched therebetween; and    said divided cache data memory modules are grouped into two and disposed on both sides of said divided TAG memory modules.    
     
     
         4 . The semiconductor integrated circuit according to  claim 3 , wherein the input/output circuits of one of the two groups of caches are opposed to the input/output circuits of the TLB, said input/output circuits being disposed on both sides of a longitudinal arrangement direction of the TLB TAG modules and the TLB data memory modules with the TLB TAG modules and the TLB data memory modules being sandwiched therebetween.  
     
     
         5 . A semiconductor integrated circuit including cache memory comprising a plurality of data memory modules, wherein 
 first and second power supply lines are provided in a layer under output signal lines connected to the output of the data memory module section, and    said first and second power supply lines intersect said output signal lines at a right angle and are alternately and repeatedly provided.    
     
     
         6 . The semiconductor integrated circuit according to  claim 5 , wherein said first and second power supply lines are provided in a layer above said output signal lines, and said first and second power supply lines intersect said output signal lines at a right angle and are alternately and repeatedly provided.  
     
     
         7 . The semiconductor integrated circuit according to  claim 5  or  6 , wherein a power-supply potential is provided to said first power supply line, a ground potential is provided to said second power supply line, a P-channel MOS transistor is provided in a layer under said first power supply line, a gate of said P-channel MOS transistor is connected to said second power supply line, a drain and a source of said P-channel MOS transistor are connected to said first power supply line, an N-channel MOS transistor is provided in a layer under said second power supply line, a gate of said N-channel MOS transistor is connected to said first power supply line, and a drain and a source of said N-channel MOS transistor are connected to said second power supply line.  
     
     
         8 . The semiconductor integrated circuit according to any of  claims 5  to  7 , wherein no other signal line is provided in parallel to all or part of said output signal lines in a layer above or below or adjacent to said output signal lines.  
     
     
         9 . The semiconductor integrated circuit according  claim 8 , wherein said first or second power supply line is provided in parallel to all or part of said output signal line between said output signal line and another signal line.  
     
     
         10 . The semiconductor integrated circuit according to any of  claims 5  to  9 , wherein said semiconductor integrated circuit has a plurality of outputs as the output of said data memory module, said outputs comprise pairs of non-inverse and inverse signals, and each set of signal lines connected to each pair of said pairs of non-inverse and inverse outputs is provided between said first and second power supply lines.  
     
     
         11 . The semiconductor integrated circuit according to any of  claims 5  to  10 , wherein the output from said data module is output to said output signal lines through a first sense amplifier.  
     
     
         12 . The semiconductor integrated circuit according to  claim 11 , wherein a given signal is selected from the plurality of data module outputs and output through a second sense amplifier.