Method and apparatus for implementing high speed signals using differential reference signals

Abstract

A device contains a first device and a second device. In one embodiment, the first device drives at least three signals, a first reference signal, and a second reference signal. The second device, which is coupled to the first device, receives the at least three signals, the first reference signal, and the second reference signal. The second device identifies values for the at least three signals according to the first reference signal and the second reference signal.

We claim:  
     
         1 . A device comprising: 
 a first device configured to drive at least three signals, a first reference signal, and a second reference signal; and    a second device coupled to the first device and configured to receive the at least three signals, the first reference signal, and the second reference signal, the second device further configured to identify values for the at least three signals according to the first reference signal and the second reference signal.    
     
     
         2 . The device of  claim 1 , further comprising a storage device coupled to the second device and configured to store output signals from the second device.  
     
     
         3 . The device of  claim 2 , wherein the storage device includes a plurality of static latches.  
     
     
         4 . The device of  claim 1 , wherein the first device is a driver, which further includes a plurality of driver circuits.  
     
     
         5 . The device of  claim 1 , wherein the second device is a receiver, which further includes a plurality of receiver circuits.  
     
     
         6 . The device of  claim 5 , wherein each receiver circuit receives a signal, a first reference signal, and a second reference signal.  
     
     
         7 . The device of  claim 5 , wherein the receiver circuit is a P-sense amplifier receiver.  
     
     
         8 . The device of  claim 1 , wherein the first reference signal is a high reference signal and the second reference signal is a low reference signal.  
     
     
         9 . The device of  claim 1 , wherein the at least three signals are data signals.  
     
     
         10 . A method comprising: 
 driving at least three signals, a first reference signal, and a second reference signal;    receiving the at least three data signals, the first reference signal, and the second reference signal; and    identifying values of the at least three signals according to the first reference signal and the second reference signal.    
     
     
         11 . The method of  claim 10 , further comprising amplifying the values of the at least three data signals.  
     
     
         12 . The method of  claim 10 , further comprising storing the values of the at least three data signals in a storage device.  
     
     
         13 . The method of  claim 10 , wherein the identifying values of the at least three signals further includes: 
 sensing a voltage swing of one of the at least three signals when voltage changes approximately one hundred millivolts; and    identifying a logic value corresponding to the voltage swing of one of the at least three signals in response to the first reference signal and the second reference signal.    
     
     
         14 . The method of  claim 10 , where the driving at least three signals, a first reference signal, and a second reference signal further includes: 
 driving the first reference signal to high; and    driving the second reference signal to low.    
     
     
         15 . A system comprising: 
 a processor;    a memory coupled to the processor;    a driver coupled to the processor and configured to drive a plurality of grouped signals, each grouped signals further including at least three signals, a high reference signal, and a low reference signal; and    a receiver coupled to the driver and configured to receive the plurality of grouped signals.    
     
     
         16 . The system of  claim 15 , further comprising a storage device coupled to the receiving device and configured to store outputs of the receiver.  
     
     
         17 . The system of  claim 16 , wherein the storage device includes a plurality of static latches.  
     
     
         18 . The system of  claim 15 , wherein the driver includes a plurality of driver circuits.  
     
     
         19 . The system of  claim 13 , wherein the receiver includes a plurality of receiver circuits.  
     
     
         20 . The system of  claim 19 , wherein the each receiver circuit receives a signal, a high reference signal, and a low reference signal and identifies a logic value of the signal in response to the high reference signal and the low reference signal.  
     
     
         21 . A system comprising: 
 a first device having a plurality of wires for transporting signals;    a second device coupled to the first device and configured to perform a pre-charge function at a receiving end of the first device; and    a third device coupled to the first device and configured to equalize potentials between the plurality of wires at a driving end of the first device.    
     
     
         22 . The system of  claim 21 , further comprising a driver coupled to the driving end of the first device and configured to drive the signals onto the plurality of wires.  
     
     
         23 . The system of  claim 21 , further comprising a receiver coupled to the receiving end of the first device and configured to receive the signals across the plurality of wires.  
     
     
         24 . The system of  claim 23 , wherein the receiver further includes at least one sensing amplifier.  
     
     
         25 . The system of  claim 24 , wherein the sensing amplifier receives a signal, a first reference signal, and a second reference signal.  
     
     
         26 . The system of  claim 25 , wherein the first reference signal is a high reference signal and the second reference signal is a low reference signal.  
     
     
         27 . The system of  claim 21 , wherein the second device is a pre-charge circuit and the third device is an equalizer circuit.  
     
     
         28 . A system comprising: 
 a first device configured to drive at least three signals, a first reference signal, and a second reference signal onto a plurality of wires;    a second device coupled to the first device and configured to receive the at least three signals, the first reference signal, and the second reference signal from the plurality of wires, the second device further configured to identify values for the at least three signals according to the first reference signal and the second reference signal;    a third device coupled to the second device and configured to perform a pre-charge function on the plurality of wires closer to receiving end of the second device; and    a fourth device coupled to the first device and configured to perform a equalizer function on the plurality of wires closer to driving end of the first device.    
     
     
         29 . A method comprising: 
 pre-charging wire potentials at a receiving end of a plurality of wires, which transports a plurality of signals across the wires, during pre-charge phase; and    equalizing wire potentials at a driving end of the plurality of wires during pre-charge phase.    
     
     
         30 . A circuit comprising: 
 a first device configured to receive a signal from a driver;    a second device coupled to the first device and configured to receive a first reference signal and a second reference signal from the driver; and    a third device coupled to the first block and configured to output at least one output signal in response to the signal, the first, and second reference signals.