Method and apparatus for providing a single-instruction multiple data digital camera system that integrates on-chip sensing and parallel processing

Abstract

A single-chip digital camera system is described. In one embodiment, the single-chip digital camera system includes a sensor array including rows and columns of discrete sensor elements, corresponding analog-to-digital converters to convert analog values into digital data, a storage element coupled to the analog-to-digital converters, to store the digital data, and a plurality of arithmetic logic units coupled to the storage element, to operate on the digital data. The digital camera system also includes a switching matrix which is coupled between the array of analog-to-digital converters and the memory element. The switching matrix spatially rotates the analog-to-digital converter outputs for storing such outputs in the memory element.

What is claimed is:  
     
         1 . A single chip digital camera system, comprising: 
 a sensor array including rows and columns of discrete sensor elements;    analog-to-digital converters to convert analog values into digital data, each coupled to a corresponding column of sensor elements;    a storage element coupled to the analog-to-digital converters, to store the digital data; and    a plurality of arithmetic logic units coupled to the storage element, to operate on the digital data.    
     
     
         2 . The single chip digital camera system of  claim 1  further comprising a switching matrix coupled between the analog-to-digital converters and the memory element, to provide spatial rotation of the digital data.  
     
     
         3 . The single chip digital camera system of  claim 1  further comprising storage registers coupled to receive the digital data from the outputs of the analog-to-digital converters, the storage registers being implemented to fit within a pitch of a column.  
     
     
         4 . The single chip digital camera system of  claim 3  further comprising a switching matrix coupled between the analog-to-digital converters and the memory element, the switching matrix to spatially rotate the digital data from the storage registers that fit within a pitch of the column to the memory element that fits within a pitch of multiple columns.  
     
     
         5 . The single chip digital camera system of  claim 1  wherein the discrete sensor elements are complementary metal-oxide semiconductor elements.  
     
     
         6 . The single chip digital camera system of  claim 1  wherein each arithmetic logic unit is coupled to adjacent arithmetic logic units to pass data therebetween.  
     
     
         7 . The single chip digital camera system of  claim 1  further comprising a first-in first-out device coupled to receive the output of one or more arithmetic logic units.  
     
     
         8 . The single chip digital camera system of  claim 1  further comprising an input/output interface coupled to the first-in first out device and the arithmetic logic units, the input/output interface to multiplex between the first-in first out output and the arithmetic logic unit outputs.  
     
     
         9 . A digital camera system, comprising: 
 a plurality of block-columns, each including, 
 rows and columns of pixel sensor elements, the pixel sensor elements to capture an image and provide a signal representation thereof,  
 analog-to-digital converters, each coupled to a corresponding column of sensor elements, each analog-to-digital converter to provide a digital value, responsive to the outputs of the sensor elements,  
 a storage element coupled to receive the digital value, and  
 an arithmetic logic unit coupled to the storage element.  
   
     
     
         10 . The single chip digital camera system of  claim 9  wherein each block-column further comprises a switching matrix coupled between the analog-to-digital converters and the memory element, the switching matrix to provide spatial rotation of the digital data.  
     
     
         11 . The single chip digital camera system of  claim 9  wherein each block-column further comprises storage registers coupled to receive the digital data from the outputs of the analog-to-digital converters, the storage registers being implemented to fit within a pitch of a column.  
     
     
         12 . The single chip digital camera system of  claim 11  wherein each block-column further comprises a switching matrix coupled between the analog-to-digital converters and the memory element, the switching matrix to spatially rotate the digital data from the storage registers that fit within a pitch of the column to the memory element that fits within a pitch of multiple columns.  
     
     
         13 . The single chip digital camera system of  claim 9  wherein the discrete sensor elements are complementary metal-oxide semiconductor elements.  
     
     
         14 . The single chip digital camera system of  claim 9  wherein the arithmetic logic unit in each block-column is coupled to arithmetic logic units in adjacent block-columns to pass data therebetween.  
     
     
         15 . The single chip digital camera system of  claim 9  wherein each block-column further comprises a first-in first-out device coupled to receive the output of the arithmetic logic unit.  
     
     
         16 . The single chip digital camera system of  claim 9  wherein each block-column further comprises a second storage element and a second arithmetic logic unit.  
     
     
         17 . The single chip digital camera system of  claim 16  wherein the arithmetic logic units of a first set of adjacent block-columns are coupled together and the second arithmetic logic units of a second set of adjacent block-columns are coupled together, wherein the first and second sets of adjacent block-columns are different.  
     
     
         18 . The single chip digital camera system of  claim 9  further comprising control circuitry, said control circuitry to control the block-columns in parallel.  
     
     
         19 . A digital camera system method, comprising: 
 providing rows and columns of discrete sensor elements, to capture an image and provide an analog representation thereof;    converting each analog representation of each column into a digital value;    storing the digital values; and    operating on the digital values in parallel to provide an output image.    
     
     
         20 . A single chip digital camera system, comprising: 
 a sensor array including rows and columns of discrete sensor elements;    analog-to-digital converter means coupled to a corresponding column of sensor elements, for converting analog values into digital data;    storage means coupled to the analog-to-digital converter means, for storing the digital data; and    arithmetic logic unit means coupled to the storage means, for performing operations on the digital data.    
     
     
         21 . The single chip digital camera system of  claim 20  further comprising switching means coupled between the analog-to-digital converter means and the memory means, for spatially rotating the digital data.  
     
     
         22 . The single chip digital camera system of  claim 20  further comprising storage means for storing the digital data from the outputs of the analog-to-digital converter means, the storage means being implemented to fit within a pitch of a column.  
     
     
         23 . The single chip digital camera system of  claim 20  wherein each arithmetic logic unit means is coupled to adjacent arithmetic logic unit means' for transferring data therebetween.