Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
Abstract
An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A dual damascene structure for electrically interconnection to a base metal interconnect structure formed in a semiconductor substrate, which comprises:
a first dielectric layer formed from a first low-K organic dielectric material over the substrate to cover the exposed surface of the base metal interconnect structure; an etch-stop layer formed from a low-K inorganic dielectric material over the first dielectric layer; a second dielectric layer formed from a second low-K organic dielectric material over the etch-stop layer; and a pair of metal plugs including a first metal plug and a second metal plug, the first metal plug penetrating successively through the second dielectric layer, the etch-stop layer, and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate, and the second metal plug penetrating through the second dielectric layer to come into contact with the etch-stop layer.
2 . The dual damascene structure of claim 1 , wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each Flare.
3 . The dual damascene structure of claim 1 , wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each SILK.
4 . The dual damascene structure of claim 1 , wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each Parylene.
5 . The dual damascene structure of claim 1 , wherein the first and second organic dielectric materials used to form the first and second dielectric layers are each BCB.
6 . The dual damascene structure of claim 1 , herein the inorganic dielectric material used to form the etch-stop layer is FSG.
7 . The dual damascene structure of claim 1 , wherein the inorganic dielectric material used to form the etch-stop layer is fluorosilicate oxide.
8 . The dual damascene structure of claim 1 , wherein the inorganic dielectric material used to form the etch-stop layer is HSQ.
9 . The dual damascene structure of claim 1 , further comprising:
a protective layer formed between the etch-stop layer and the second dielectric layer.
10 . The dual damascene structure of claim 9 , wherein the protective layer is formed from silicon oxide.
11 . The dual damascene structure of claim 9 , wherein the protective layer is formed from silicon-oxy-nitride.
12 . The dual damascene structure of claim 9 , wherein the protective layer is formed from silicon nitride.
13 . The dual damascene structure of claim 1 , further comprising:
a hard mask layer formed over the second dielectric layer.
14 . The dual damascene structure of claim 13 , wherein the hard mask layer is formed from silicon oxide.
15 . The dual damascene structure of claim 13 , wherein the hard mask layer is formed from silicon-oxy-nitride.
16 . The dual damascene structure of claim 13 , wherein the hard mask layer is formed from silicon nitride.
17 . A dual damascene structure for electrically interconnection to a base metal interconnect structure formed in a semiconductor substrate, which comprises:
a first dielectric layer formed from a first low-K inorganic dielectric material over the substrate to cover the exposed surface of the base metal interconnect structure: an etch-stop layer formed from a low-K organic dielectric material over the first dielectric layer; a second dielectric layer formed from a second low-K inorganic dielectric material over the etch-stop layer; and a pair of metal plugs including a first metal plug and a second metal plug, the first metal plug penetrating successively through the second dielectric layer, the etch-stop layer, and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate, and the second metal plug penetrating through the second dielectric layer to come into contact with the etch-stop layer.
18 . The dual damascene structure of claim 17 , wherein the organic dielectric material used to form the etch-stop layer is Flare.
19 . The dual damascene structure of claim 17 , wherein the organic dielectric material used to form the etch-stop layer is SILK.
20 . The dual damascene structure of claim 17 , wherein the organic dielectric material used to form the etch-stop layer is Parylene.
21 . The dual damascene structure of claim 17 , wherein the organic dielectric material used to form the etch-stop layer is BCB.
22 . The dual damascene structure of claim 17 , wherein the first and second inorganic dielectric materials used to form the first and second dielectric layers are each FSG.
23 . The dual damascene structure of claim 17 , wherein the first and second inorganic dielectric materials used to form the first and second dielectric layers are each fluorosilicate oxide.
24 . The dual damascene structure of claim 17 , wherein the first and second inorganic dielectric materials used to form the first and second dielectric layers are each HSQ.
25 . The dual damascene structure of claim 17 , further comprising:
a protective layer formed between the etch-stop layer and the second dielectric layer.
26 . The dual damascene structure of claim 25 , wherein the protective layer is formed from silicon oxide.
27 . The dual damascene structure of claim 25 , wherein the protective layer is formed from silicon-oxy-nitride.
28 . The dual damascene structure of claim 25 , wherein the protective layer is formed from silicon nitride.Join the waitlist — get patent alerts
Track US2003189254A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.