Structure and method for evaluating an integrated electronic device

Abstract

The structure allows checking an integrated electronic device comprising an oxide layer to be measured located above a doped pocket of a wafer of doped semiconductor material and arranged adjacent to a gate region of polycrystalline semiconductor material. The structure is formed at a suitable point of the wafer and comprises an oxide test region of the same material, having the same thickness and the same electrical characteristics as the oxide layer to be measured and a polycrystalline region of the same material, having the same thickness and the same electrical characteristics as the gate region. The polycrystalline region extends preferably along the perimeter of a square and delimits laterally the oxide test region, the area of which is greater than the area of the oxide layer to be measured so as to allow non-destructive testing, on-line, of the oxide layer to be measured during an early stage of the manufacturing process.

1 . A structure for checking an integrated electronic device comprising: 
 an oxide layer to be measured located above a body of doped semiconductor material and arranged in a position adjacent to a gate region of polycrystalline semiconductor material, said oxide layer having a first area;    an oxide test region of the same material as said oxide layer and having the same thickness and the same electrical characteristics as said oxide layer; and    a polycrystalline region of the same material as said gate region, having the same thickness and the same electrical characteristics as said gate region, and positioned adjacent to the oxide test region, said oxide test region having a second area greater than the first area.    
     
     
         2 . A structure according to  claim 1  wherein said polycrystalline region extends along a closed line.  
     
     
         3 . A structure according to  claim 2  wherein said closed line delimits an area with dimensions greater than 50×50 μm 2 .  
     
     
         4 . The structure according to  claim 1  wherein said polycrystalline region laterally surrounds and delimits said oxide test region.  
     
     
         5 . A structure for checking an integrated electronic device, comprising: 
 a doped semiconductor material body;    a gate region of polycrystalline semiconductor material;    an oxide layer having a thickness to be determined, located above the semiconductor material body, arranged in a position adjacent to the gate region, and having a first area; and    a test region positioned on the semiconductor material body, the test region including an oxide test region of a same material as the oxide layer and having a thickness that is equal to the thickness of the oxide layer, the oxide test region having a second area that is greater than the first area and sufficiently large to be measured in a non-destructive manner by an ellipsometer.    
     
     
         6 . The structure of  claim 5  wherein the test region further includes a polycrystalline region that completely surrounds the oxide test region.  
     
     
         7 . The test structure of  claim 6  wherein the polycrystalline region extends along a closed line.  
     
     
         8 . The test structure of  claim 5  wherein the second area has dimensions greater than or equal to 50×50 μm 2 .