Timing signal occurrence circuit

Abstract

Object of the present invention is to provide a timing signal occurrence circuit capable of precisely adjusting timing, without complicating a circuit. A timing signal occurrence circuit according to the present invention has a tristate buffer connected to a delay clock line, a tristate buffer connected to an operand bus, a calculator connected to an input terminal of each of the tristate buffers, a pulse generating circuit for generating an one shot pulse based on a delay clock on the delay clock line, and a calculator for fetching operands on the operand bus and carrying out calculation using the fetched operands. Either of a plurality of tristate buffers is arbitrarily selected to adjust delay time of the delay clock. Because of this, it is possible to generate a one shot pulse with optimum timing for carrying out calculation by the calculator.

What is claimed is:  
     
         1 . A timing signal occurrence circuit, comprising: 
 a plurality of signal output circuits configured to output a timing signal, and    a selecting circuit configured to select either one of said signal output circuits,    wherein output terminals of all of said signal output circuits are connected to a common timing signal line, and    wherein output terminals of said signal output circuits unselected by said selecting circuit.    
     
     
         2 . The timing signal occurrence circuit according to  claim 1 , 
 wherein said signal output circuits is provided in accordance with a subject adjustment circuit being a subject for timing adjustment, and    wherein said selecting circuit selects either one of said signal output circuits based on the delay time of a critical path of said subject adjustment circuit.    
     
     
         3 . The timing signal occurrence circuit according to  claim 1 , further comprising: 
 a calculator configured to fetch operands on an operand bus and to carry out the fetched operands, in sync with a delay clock on a delay clock line;    a clock delay adjustment circuit configured to adjust delay of the delay clock on said delay clock line, and    an operand delay adjustment circuit configured to adjust delay of the operands on said operand bus,    wherein said clock delay adjustment circuit is provided with said signal output circuit configured to output said delay clock with timing different from each other,    wherein said operand delay adjustment circuit is provided with said signal output circuits configured to output the operands with timing different from each other, and    wherein each of said clock delay adjustment circuit and said operand control circuit selects either of said signal output circuit, so that said calculator fetches the operands after the operand on said operand bus is settled.    
     
     
         4 . The timing signal occurrence circuit according to  claim 1 , 
 wherein each of said signal output circuits has a tristate buffer configured to switch whether to output a signal from an output terminal or to set the output terminal to be high impedance state, based on logic of a control terminal, and    wherein said selecting circuit switches logic of said control terminal.    
     
     
         5 . The timing signal occurrence circuit according to  claim 3 , 
 wherein each of said signal output circuit has a tristate buffer configured to switch whether to output a signal from an output terminal or to set the output terminal to be high impedance state,    wherein said selecting circuit switches logic of said control terminal,    wherein said delay adjustment circuit adjusts the delay time based on wiring resistor and wiring capacitance of said delay clock line and said transfer buffer, and    wherein said operand delay adjustment circuit adjusts the delay time based on the wiring resistance and the wiring capacitance of said operand bus and said tristate buffer.    
     
     
         6 . The timing signal occurrence circuit according to  claim 3 , further comprising a plurality of transistors connected to said delay clock line, these transistors being turned on in order to set said delay clock line to a prescribed voltage level when said delay clock is in a prescribed logic.  
     
     
         7 . The timing signal occurrence circuit according to  claim 3 , further comprising a plurality of transistors connected to said operand bus, these transistors being turned on in order to set said operand bus to a prescribed voltage level when said delay clock is in a prescribed logic.  
     
     
         8 . The timing signal occurrence circuit according to  claim 3  further comprising a switch connected to said control terminal of said tristate buffer, 
 wherein said tristate buffer outputs said delay clock when said switch is in a first change-over state, and becomes high impedance state when said switch is in a second change-over state.  
 
     
     
         9 . The timing signal occurrence circuit according to  claim 4 , 
 wherein the dummy load for timing control is used as said tristate buffer.    
     
     
         10 . The timing signal occurrence circuit according to  claim 4 , further comprising a selecting control circuit configured to control selection by said selecting circuit.  
     
     
         11 . The timing signal occurrence circuit according to  claim 10 , 
 wherein said selecting control circuit has a register with the number of bits in accordance with the number of said tristate buffers.    
     
     
         12 . A timing signal selecting circuit, comprising: 
 a plurality of memory cells connected to word lines and bit lines;    a plurality of dummy circuits connected to the word line an the bit line different from each other, and    a sense amplifier configured to amplify data read out from the selected memory cell,    wherein driving timing of said sense amplifier is controlled based on signal propagation time of each of said dummy circuits.    
     
     
         13 . The timing signal occurrence circuit according to  claim 12 , 
 wherein said memory cells constitute cell blocks, said dummy circuit being provided between each of said cell blocks.    
     
     
         14 . The timing signal occurrence circuit according to  claim 12 , 
 wherein driving timing of said sense amplifier is set so as to be able to correctly read out from said sense amplifier data passing through each of said dummy circuits.    
     
     
         15 . The timing signal occurrence circuit according to  claim 12 , 
 wherein said dummy circuit is consisted of a plurality of transistors connected in parallel to the corresponding word line and bit line.    
     
     
         16 . The timing signal occurrence circuit according to  claim 15 , 
 wherein said memory cells constitute cell blocks, said dummy circuit being provided between said cell blocks, and    wherein the number of the transistors in said dummy circuit is set in accordance with the number of the transistors in said cell block.    
     
     
         17 . The timing signal occurrence circuit according to  claim 12 , 
 wherein at least one of said dummy circuits is a critical path.