Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration

Abstract

First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

What is claimed is:  
     
         1 . A non-volatile semiconductor memory device comprising: 
 a semiconductor body of a first conductivity type;    first and second semiconductor regions of a second conductivity type, formed apart from each other on the semiconductor body;    a stacked gate formed on the semiconductor body between the first and second semiconductor regions, with a gate insulating film inserted therebetween, the stacked gate having a first side surface, a second side surface opposed to the first side surface, and an upper surface;    an interlayer insulating film formed above the semiconductor body;    a contact material buried to be adjacent to the first side surface of the stacked gate, in the interlayer insulating film, the contact material contacting the first semiconductor region;    a first insulating film formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material; and    a second insulating film formed on the first side surface adjacent to the contact material, and the first insulating film.    
     
     
         2 . The device according to  claim 1 , wherein the stacked gate includes a charge storage layer on the gate insulating film, a control gate on the charge storage layer, a cap insulating film on the control gate, and the first side surface of the stacked gate includes side surfaces of the charge storage layer, the control gate, and the cap insulating film.  
     
     
         3 . The device according to  claim 2 , wherein the first insulating film is made of a material different from the cap insulating film, and the second insulating film is made of the same material as the cap insulating film.  
     
     
         4 . The device according to  claim 2 , wherein the contact material has a side surface, the side surface contacts the second insulating film, and a part of the side surface extends over the cap insulating film.  
     
     
         5 . The device according to  claim 1 , wherein the first insulating film is an oxide-based insulating film having a film thickness of 200 Å or less, and the second insulating film is a nitride-based insulating film having a film thickness of 400 Å or less.  
     
     
         6 . A non-volatile semiconductor memory device comprising: 
 a semiconductor body of a first conductivity type;    first and second semiconductor regions of a second conductivity type, formed apart from each other on the semiconductor body;    a stacked gate formed on the semiconductor body between the first and second semiconductor regions, with a gate insulating film inserted therebetween, the stacked gate including a charge storage layer on the gate insulating film, a control gate on the charge storage layer, and a cap insulating film on the control gate, and the stacked gate having a first side surface, a second side surface opposed to the first side surface, and an upper surface, the first and second surfaces each including side surfaces of the charge storage layer, the control gate, and the cap insulating film;    an interlayer insulating film formed above the semiconductor body;    a contact material buried to be adjacent to the first side surface of the stacked gate, in the interlayer insulating film, the contact material contacting the first semiconductor region;    a first insulating film formed on at least a part of the side surface of the control gate on the first side surface, all of the side surface of the charge storage layer; and    a second insulating film formed on the first side surface adjacent to the contact material to cover the first insulating film.    
     
     
         7 . The device according to  claim 6 , wherein the first insulating film is made of a material different from the cap insulating film, and the second insulating film is made of the same material as the cap insulating film.  
     
     
         8 . The device according to  claim 6 , wherein the contact material has a side surface, the side surface contacts the second insulating film, and a part of the side surface extends over the cap insulating film.  
     
     
         9 . The device according to  claim 6 , wherein the first insulating film is an oxide-based insulating film having a film thickness of 200 Å or less, and the second insulating film is a nitride-based insulating film having a film thickness of 400 Å or less.  
     
     
         10 . A non-volatile semiconductor memory device comprising: 
 a semiconductor body of a first conductivity type;    first and second semiconductor regions of a second conductivity type, formed apart from each other on the semiconductor body;    a stacked gate formed on the semiconductor body between the first and second semiconductor regions, with a gate insulating film inserted therebetween, the stacked gate including a charge storage layer on the gate insulating film, a control gate on the charge storage layer, and a cap insulating film on the control gate, and the stacked gate having a first side surface, a second side surface opposed to the first side surface, and an upper surface, the first and second surfaces each including side surfaces of the charge storage layer, the control gate, and the cap insulating film;    an interlayer insulating film formed above the semiconductor body;    a contact material buried to be adjacent to the first side surface of the stacked gate, in the interlayer insulating film, the contact material contacting the first semiconductor region;    a first insulating film formed on at least a part of the side surface of the control gate on the first side surface, all of the side surface of the charge storage layer on the first side surface, at least a part of the side surface of the control gate on the second side surface, and all of the side surface of the charge storage layer on the second side surface; and    a second insulating film formed on the first side surface adjacent to the contact material to cover first insulating film, the second side surface to cover first insulating film, and the upper surface.    
     
     
         11 . The device according to  claim 10 , wherein the first insulating film is made of a material different from the cap insulating film, and the second insulating film is made of the same material as the cap insulating film.  
     
     
         12 . The device according to  claim 10 , wherein the contact material has a side surface, the side surface contacts the second insulating film, and a part of the side surface extends over the cap insulating film.  
     
     
         13 . The device according to  claim 10 , wherein the first insulating film is an oxide-based insulating film having a film thickness of 200 Å or less, and the second insulating film is a nitride-based insulating film having a film thickness of 400 Å or less.  
     
     
         14 . A non-volatile semiconductor memory device comprising: 
 a plurality of element separation regions made of element separation insulating material buried in a plurality of trenches formed in a semiconductor body;    a stacked gate formed on the semiconductor body between the element separation regions, with a gate insulating film inserted therebetween, the stacked gate including a charge storage layer on the gate insulating film, a control gate on the charge storage layer, and a gap insulating film on the control gate; and    an interlayer insulating film formed above the semiconductor body;    wherein the charge storage layer is provided with a side surface thereof aligned with the element separation regions, and upper surfaces of the element separation regions below the control gate are higher than the upper surfaces of the element separation regions between control gates.    
     
     
         15 . The device according to  claim 14 , further comprising: 
 a plurality of first semiconductor regions of a first conductivity type, electrically separated from each other by the element separation regions;    second and third semiconductor regions of a second conductivity type, formed apart from each other on the first semiconductor regions;    a contact material buried in the interlayer insulating film, the contact material contacting the second semiconductor region.    
     
     
         16 . The device according to  claim 15 , wherein the upper surfaces of the element separation regions between the control gates are lower than an upper surface of the charge storage layer.  
     
     
         17 . The device according to  claim 15 , further comprising: 
 a bit line formed on the interlayer insulating film, for inputting/outputting a signal;    a source line formed on the interlayer insulating film, for inputting/outputting a signal; and    a peripheral circuit including a peripheral transistor, for controlling signals to the bit line, the source line, and the control gate, wherein 
 the peripheral transistor has a gate insulating film, a gate electrode, a source region, and a drain region, and the gate insulating film adjacent to the contact material connected to one of the source and drain regions has a film thickness smaller than that of the gate insulating film below the gate electrode.  
   
     
     
         18 . The device according to  claim 17 , wherein the stacked gate, the first, second, and third semiconductor regions construct a memory cell transistor, the peripheral transistor is a high-withstanding-voltage-based transistor for driving high voltages for writing and erasure applied to the memory cell transistor during operation of supplying/receiving charges to/from the memory cell transistor, and the gate insulating film below the gate electrode has a film thickness greater than that of the gate insulating film below the charge storage layer of the memory cell transistor.