Rapid input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it

Abstract

An input and output probe system software according to the present invention, which is performed in an arbitrary computer for server, adds an additional circuit for probe capable of the input/output prove, to the design verification and examination object circuit so as to generate an extended circuit capable of the input/output probe in an automatic system. Interface module of the input/output probe connects a hardware board, wherein the extended circuit capable of the input/output prove is embodied in a hardware chip and a computer for server. Said interface module controls the performance of the hardware board, performs the input/output prove against the hardware chip on the hardware board under the specific situation or condition, thereby enabling the exchange of information on the performance results in respect to the design verification and the examination object circuit between the computer for server and the hardware chip.

What is claimed is:  
     
         1 . An input/output probing apparatus, comprising: 
 an input/output probing system software; and    an input/output probing interface module for connecting a circuit for its design verification,    wherein said input/output probing system software generates, for the circuit for its design verification to be embodied in at least one semiconductor chip mounted on an arbitrary prototyping board or an arbitrary PCB, a HDL code for representing an additional circuit for IOP-probe or the behavior of said additional circuit for IOP-probe, and adds said HDL code for representing said additional circuit for IOP-probe or the behavior of said additional circuit for IOP-probe to said circuit for its design verification or the HDL code,    thereby making it possible to embody said circuit for its design verification capable of doing the input/output probe in said semiconductor chip and to perform said input/output probe by using HDL code for representing said additional circuit for IOP-probe or the behavior of the additional circuit for IOP-probe.    
     
     
         2 . The input/output probing apparatus according to  claim 1 , 
 wherein said HDL code for representing said additional circuit for IOP-probe or the behavior of the additional circuit for IOP-probe is automatically generated by performing said input/output probing system software.    
     
     
         3 . The input/output probing apparatus according to  claim 2 , 
 wherein before automatically generating said HDL code said input/output probing system software, the circuit for its design verification or said HDL code for its design verification is examined by the input/output probing system software; and    wherein a new circuit for its design verification or a new HDL code for its design verification, which is functionally equivalent to the original circuit or the original HDL code and which is completely synchronized with a single clock and converted to, is automatically generated to perform the input/output probe.    
     
     
         4 . The input/output probing apparatus according to  claim 2  or  claim 3 , 
 wherein said input/output probing system software additionally generates a event detector for detecting the conversion condition into a probe mode for the input/output probe to realize the event detector in the inside of said semiconductor chip.  
 
     
     
         5 . The input/output probing apparatus according to  claim 4 , further comprising an extended circuit for its design verification which is completed by adding the additional circuit for IOP-probe to the circuit for its design verification, 
 wherein in an output probe mode, said extended circuit becomes a shift register structure capable of parallel-loading a storage element for its output probe to carry out the shifting operation synchronized with a probe clock, so that the logical values of said shift register can have the logical values of the storage elements for its output probe by parallel-loading just before said shifting operation, and thus the content of a corresponding region of the memory for its output probe can be read with a reading operation;    wherein in an input probe mode, said extended circuit becomes the shift register structure capable of serial-loading a storage element for its input probe to carry out the shifting operation, and wherein a synchronous set or reset operation, or the synchronous set or reset operation subsequent to an asynchronous set or reset operation, or a synchronous disable operation subsequent to the asynchronous set or reset operation is selectively applied to each of the storage elements for its input probe by such shifting operation, thus making the logical values of the storage elements for its input probe the input probe values, and thus a corresponding region of the memory for its input probe can be written by a writing operation when necessary; and    wherein in a normal mode, a circuit, which does not change the functional logical properties of the circuit for its design verification even if the additional circuit for IOP-probe is added thereto is constructed.    
     
     
         6 . The input/output probing apparatus according to  claim 4 , further comprising an extended HDL code for its design verification which is completed by adding an additional HDL code for representing the behavior of the additional circuit for IOP-probe to the HDL code for its design verification when the circuit for its design verification object is dictated as the HDL code, 
 wherein in an output probe mode, said extended HDL code represents the behavior of the shift register, which is capable of parallel-loading the storage element for its output probe, to carry out the shifting operation synchronized with the probe clock, so that signal values of signal lines of a register HDL code can have the signal values for output probe by parallel-loading in the HDL code for representing the behavior of the shift register just before said shifting operation, and thus a specific region of the memory for its output probe can be read by a reading operation;    wherein in an input probe mode, said extended HDL code becomes the shift register structure, which is capable of serial-loading with the storage element for its input probe, to carry out the shifting operation synchronized with the probe clock, wherein the synchronous set or reset operation, or the synchronous set or reset operation subsequent to the asynchronous set or reset operation, or the synchronous disable operation subsequent to the asynchronous set or reset operation is applied to the signals of the HDL code by such shifting operation, the HDL code representing the behavior of storage elements of the HDL code for its input probe, thus making the logic values of signals for input probe the input probe values, and thus a corresponding region of the memory for its input probe can be written by the writing operation when necessary; and    wherein in the normal mode, a HDL code, which does not change the behavior of the HDL code for its design verification changed even if the additional circuit for IOP-probe is added to the HDL code for its design verification, is constructed.    
     
     
         7 . The input/output probing apparatus according to  claim 5  or  6 , 
 wherein in the output probe mode, the extended circuit for its design verification added with the additional circuit for IOP-probe become at least one shift register array structure capable of parallel-loading the storage elements for output probe by the signals for output probe and the double input flip-flops together with the circuit for its design verification assigned to the RFPD for output probe, while one input by said each of the double input flip-flops is connected to the signal lines for probe in order that each of the signal lines for probe can be loaded in parallel into said double input flip-flop; the output of a single flip-flop existing in each one of at least one shift register array structure is logically connected, respectively, to one of at least one output probe line of said RFPD at the time of the output probe; additionally when necessary, for the memory for output probe, the output of a single flip-flop existing in the respective shift register array structures which store the contents read by the reading operation of the corresponding region by the finite state machine for memory probe embedded in the corresponding RFPD, is appeared on at least one output probe line of said RFPD by the shift operation;  
 wherein in the input probe mode, the input of a single flip-flop existing in each one of at least one shift register array structure capable of parallel-loading the storage elements for input probe is logically connected, respectively, to one of at least one input probe line of said RFPD in order that the input probe values can be loaded in series into the shift register by the shifting operation synchronized with the probe clock; in case that a user clock is connected to clock input of the respective storage elements driving each of the signals for input probe, the output of the respective flip-flops constructing at least one shift register array capable of said parallel-load is connected to a single input of each of the double input storage elements replaced for each of the corresponding storage elements, or a combination circuit is added to a data input terminal of said storage element in order that each of the corresponding storage elements becomes a synchronous set or synchronous reset by the output value of the respective flip-flops constructing at least one shift register array capable of said parallel-load; in case where the user clock is not physically connected to the clock input of the corresponding storage element for each of the storage elements deriving each of the signal lines for input probe, the corresponding storage element is constituted as a storage element having an asynchronous set and asynchronous reset, and the combination circuit for controlling the asynchronous set input and asynchronous reset input of said storage element is added, so that the logical value of said storage element can be established as a specific input probe value desired through a process including the asynchronous set or asynchronous reset operation for said storage element; additionally when necessary, for the memory for input probe, the logical values are assigned from at least one input probe line of said RFPD to each of the inputs of the first terminal flip-flop existing in each of the shift register array structures in the memory data input terminal by the shifting operation, in order that after the shifting operation of the shift register in said memory data input terminal is completed, the input probe for the memory can be performed in the writing operation to said specific address of the memory by the subsequent finite state machine for memory probe, the memory having the contents to be written in the specific address by the writing operation of the corresponding region.  
 
     
     
         8 . The input/output probing apparatus according to  claim 5  or  6 , 
 wherein the shift register array of the additional circuit for IOP-probe is constructed by connecting double input flip-flops in series, or the HDL code corresponding to the behavior of shift register array of the HDL code representing the behavior of the additional circuit for IOP-probe is constructed as the HDL code representing the behavior of double input flip-flops in series.  
 
     
     
         9 . The input/output probing apparatus according to  claim 8 , wherein a physically identical probe clock is assigned to all clock inputs of the double input flip-flops of the shift register array of the additional circuit for IOP-probe, and the control over the probe clock and at least one user's clock is performed by an interface module for its input/output probe and the input/output probing system software.  
     
     
         10 . The input/output probing apparatus according to  claim 7 , wherein the output probe line and the input probe line exist as individually independent unidirectional probe lines.  
     
     
         11 . The input/output probing apparatus according to  claim 7 , wherein the output probe line and the input probe line exist as bi-directional probe lines in which the output probe line and the input probe line are mutually combined.  
     
     
         12 . A combined verification apparatus of emulation and simulation, comprising an input/output probing system software capable of automatically generating an additional circuit for IOP-probe and an interface module of the input/output probe, wherein the emulation and simulation are alternately performed.  
     
     
         13 . The input/output probing apparatus according to  claim 12 , wherein the input/output probing system software can automatically generate a detector of the input/output probe point.  
     
     
         14 . An input/output probing method using an input probe method, 
 wherein in a circuit for its design verification for input probe, for the input probe of at least one flip-flop, in which a user clock is not directly assigned to a clock input of at least one flip-flop existing in the circuit for its design verification; rather, a locally generated local clock or gated clock is inputted thereto, there is generated the extended circuit for its design verification by adding a finite state machine, which generates a shift register array structure capable of serial-load and asynchronous set/reset enabling signals at a specific point of time and then outputs them, and the additional circuit for input probe having a control circuit to the circuit for its design verification;    wherein in input probe mode, after loading input probe values to said shift register array structure from the outside in order via the serial-loading synchronized with the probe clock, there are generated an input probe value of flip-flops to be an corresponding input probe object among the input probe values loaded to the respective flip-flops of said shift register array; an asynchronous set/reset enabling output value for the flip-flop to be said input probe object, the asynchronous set/reset enabling output value being generated from said finite state machine; and signal values for controlling the asynchronous set and reset of the flip-flop, so that the input probe is accomplished by said signal values in the input probe mode through a process including the operation for controlling the asynchronous set and reset inputs of the flip-flop for input probe; and    wherein in normal operation mode, the extended circuit for its design verification generated by adding said additional circuit for input probe to the original circuit for its design verification can perform the operation functionally equivalent to the original circuit for its design verification.    
     
     
         15 . A combined verification method of emulation and simulation, wherein an emulation method for verifying the extended circuit for its design verification realized by adding an additional circuit for IOP probe to a circuit for its design verification by at least one semiconductor chip, and a simulation method for verifying the circuit for its design verification by a simulator are alternately performed at least once when necessary, through the exchange of the state information in an automatic method between an arbitrary prototyping board or an arbitrary PCB and an arbitrary simulator, by performing the input/output probe for at least one semiconductor chip.  
     
     
         16 . The combined verification method of emulation and simulation according to  claim 15 , wherein the exchange of the complete state information in the automatic method between the arbitrary prototyping board or PCB and the arbitrary simulator is used by the input/output probe based on the additional circuit for IOP-probe.  
     
     
         17 . The combined verification method of emulation and simulation according to  claim 15 , wherein the exchange of the partial state information in the automatic method between the arbitrary prototyping board or PCB and the arbitrary simulator is used by the input/output probe based on the additional circuit for IOP-probe.  
     
     
         18 . A combined verification method of emulation and simulation, comprising the steps of: 
 preparing the performance of simulation of a circuit for its design verification using an arbitrary simulator in a server computer, where the circuit for its design verification and the name of ASIC vendor library used at the time of the design are inputted by the server computer, and then, the extended circuit for its design verification added with an additional circuit for IOP-probe capable of input/output probe is generated in an automatic method by an input/output probing system software, thereby realizing said extended design verification object circuit in a prototyping board on which at least one semiconductor chip is equipped;    determining the present execution mode, where the initial state information of the circuit for its design verification to be a combined verification object is inputted by the server computer in order that the present state information of a simulation circuit for said arbitrary simulator and an emulation circuit in said arbitrary prototyping board or arbitrary PCB would be the same as the initial state information of the circuit for its design verification, thereby determining whether the first performance is carried out by simulation or emulation; and determining the execution mode switching conditions between simulation and emulation under the execution process and storing the determined execution mode switching condition in the execution mode switching condition queue in time order, and then, making the first queue the conversion point and the conversion condition of the present verification method;    proceeding with the design verification by either of the emulation or simulation, which should be suitable for the present execution mode;    performing the design verification which is different from the conventional design verification method but subsequent to the conventional design verification method, through the exchange of the present state information, by an input/output probing method using the additional circuit for IOP-probe realized in at least one semiconductor chip equipped on said arbitrary prototyping board or arbitrary PCB and an input/output probing apparatus, where the performance of the present design verification method is stopped at the point when the conversion point or conversion condition of the present verification method is satisfied; new conversion point and conversion condition of the present verification method are established in the execution mode switching queue; the present execution mode is converted to different execution mode to execute the emulation; and    continuing to alternately perform at least once the design verification method as above between emulation and simulation till the execution mode switching queue is vacant.    
     
     
         19 . A combined verification method of emulation and simulation, comprising the steps of: 
 preparing the performance of simulation of a circuit for its design verification using an arbitrary simulator in a server computer, where the circuit for its design verification and the name of ASIC vendor library used at the time of the design are inputted by the server computer, and then, the extended circuit for its design verification added with an additional circuit for IOP-probe capable of input/output probe is generated in an automatic method by an input/output probing system software, thereby realizing said extended design verification object circuit in a prototyping board on which at least one semiconductor chip is equipped;    determining the present execution mode, wherein the initial state information of the circuit for its design verification to be a combined verification object is inputted by the server computer in order that the present state information of a simulation circuit for said arbitrary simulator and an emulation circuit in said arbitrary prototyping board or arbitrary PCB would be the same as the initial state information of the circuit for its design verification, thereby determining whether the first performance is carried out by simulation or emulation; and determining the execution mode switching conditions between simulation and emulation under the execution process and storing the determined execution mode switching condition in the execution mode switching condition queue in time order, and then, making the first queue the conversion point and the conversion condition of the present verification method;    proceeding with the design verification by either of the emulation or simulation, which should be suitable for the present execution mode;    performing the design verification which is different from the conventional design verification method but subsequent to the conventional design verification method, through the exchange of the present state information, by an input/output probing method using the additional circuit for IOP-probe realized in at least one semiconductor chip equipped on said arbitrary prototyping board or arbitrary PCB and an input/output probing apparatus, where the performance of the present design verification method is stopped at the point when the conversion point or conversion condition of the present verification method is satisfied; new conversion point and conversion condition of the present verification method are established in the execution mode switching queue; the present execution mode is converted to different execution mode to execute the emulation; and    continuing to alternately perform at least once the design verification method as above between emulation and simulation till the execution mode switching queue is vacant.    
     
     
         20 . A combined verification method of emulation and simulation, comprising the steps of: 
 preparing the performance of simulation of a HDL code for its design verification by an arbitrary simulator in a server computer, where the HDL code for its design verification is inputted by the server computer, and then, an extended HDL code for its design verification added with an additional HDL code for IOP-probe capable of input/output probe is generated in an automatic method by an input/output probing system software, thereby realizing said extended HDL code for its design verification in a prototyping board on which at least one semiconductor chip is equipped;    determining the present execution mode, where the initial state information of the HDL code for its design verification to be a combined verification object is inputted by the server computer in order that the present state information of a simulation HDL code for said arbitrary simulator and an emulation HDL code in said arbitrary prototyping board or arbitrary PCB would be the same as the initial state information of the HDL code for its design verification, thereby determining whether the first execution is carried out by simulation or emulation; and determining the execution mode switching conditions between simulation and emulation under the execution process and storing the determined execution mode switching condition in the execution mode switching condition queue in time order, and then, making the first queue the conversion point and the conversion condition of the present verification method;    proceeding with the design verification by either of the emulation or simulation, which should be suitable for the present execution mode;    performing the design verification which is different from the conventional design verification method but subsequent to the conventional design verification method, through the exchange of the present state information, by an input/output probing method using the additional HDL code for IOP-probe realized in at least one semiconductor chip equipped on said arbitrary prototyping board or arbitrary PCB and an input/output probing apparatus, where the performance of the present design verification method is stopped at the point when the conversion point or conversion condition of the present verification method is satisfied; new conversion point and conversion condition of the present verification method are established in the execution mode switching queue; the present execution mode is converted to different execution mode to execute the emulation; and    continuing to alternately perform at least once the design verification method as above between emulation and simulation till the execution mode switching queue is vacant.    
     
     
         21 . Input/output probing method, comprising the steps of: 
 inputting a name of ASIC vendor library and a circuit for its design verification, or a HDL code for its design verification;    inputting a signal line for its input/output probe;    generating an extended circuit for its design verification by adding an additional circuit for IOP-probe to the circuit for its design verification after the additional circuit for IOP-probe is generated according to its corresponding semiconductor chip on a prototyping board, or generating an extended HDL code for its design verification by adding an additional HDL code for IOP-probe to the HDL code for its design verification after the additional HDL code for IOP-probe is generated;    embodying the extended circuit for its design verification or the extended HDL code for its design verification in their corresponding semiconductor chips on the prototyping board;    performing a circuit verification process in a normal mode;    examining the necessity of the probe performance and whether said probe performance is an output probe;    performing an input probe by assigning data for input probe to an input probe line, via an input/output probing interface module in a server computer after converting the data for input probe generated in the server computer to the input probe mode; and    completing the output probe by transmitting a value appeared on an output probe line, the value being generated by performing the output probe after conversion of the value to the output probe mode, to the server computer via the input/output probing interface module.    
     
     
         22 . The input/output probing apparatus according to  claim 1 , wherein a semiconductor chip is FPGA, CPLD or a ASIC chip.  
     
     
         23 . The combined verification method of emulation and simulation according to any one of  claims 15  to  20 , which said simulator is a simulation accelerator.  
     
     
         24 . The combined verification method of emulation and simulation according to any one of  claims 15  to  20 , wherein said method is carried out by an input/output probing apparatus comprising: 
 an input/output probe server computer for performing a input/pout probe system software which performs the input/output probe on the prototyping board connected to the input/output probing interface module;  
 a simulation server computer for performing the simulation; and  
 a simulation accelerator server computer;  
 wherein the input/output probe server computer and the simulation server computer, or the input/output probe server computer and the simulation accelerator server computer are connected to each other, through a short/long-distance computer network or inter-network, so that they are performed in a remote method based on the input/output probing method using the input/output probing apparatus under a network environment where emulation and simulation are distributed.  
 
     
     
         25 .  
     
     
         26 .  
     
     
         27 . A combined verification method of emulation and simulation, wherein the input/output probe is made by embodying an extended circuit for its design verification added with an additional circuit for IOP-probe in at least one RFPD equipped on an arbitrary at least one prototyping board or an arbitrary PCB, 
 wherein the simulation subsequent to the emulation is possible by transmitting complete state information or partial state information, which is extracted from the extended circuit for design verification in said at least one RFPD at the time of the output probe, to a server computer via an interface module, and    wherein the emulation of the circuit for its design verification is possible subsequent to the simulation by transmitting the complete state information or the partial state information extracted from an arbitrary simulator, in which a software model of the circuit for its design verification is performed at the time of the input probe, to said at least one RFPD via the interface module.    
     
     
         28 . The combined verification method of emulation and simulation according to  claim 27 , wherein the emulation and simulation are alternately performed at least once, and at least one RFPD equipped on said at least one arbitrary prototyping board or arbitrary PCB is temporally and spatially shared among two or more variously different circuits for their design verification,  
     
     
         29 . The combined verification method of emulation and simulation according to  claim 27  or  28 , wherein the extended circuit for its design verification added with the additional circuit for IOP-probe is realized in at least one RFPD mounted on the arbitrary prototyping board or arbitrary PCB so as to make the input/output probe possible; wherein the complete state information or the partial state information is extracted in real time from the extended circuit for its design verification performed on said at least one RFPD whenever at least one output probe is periodically or non-periodically performed during the emulation, operating the circuit for its design verification included in the extended circuit for its design verification throughout the entire emulation process without stopping, and then, the extracted information is transmitted to the server computer through the interface module so as to establish at least one roll-back point; simultaneously, wherein an input sequence is sampled in real time in memory during the emulation so as to replay the emulation when necessary; wherein during a certain period of time desired by a user after the emulation is completed, some signals values for output-probing among all signals existing in the circuit for its design verification or the HDL code for its design verification is obtained by performing both the emulation using the input sequence stored in said memory and the simulation using the arbitrary simulator when necessary, through the input probe using said extracted state information as to said at least one RFPD, after making the state of the circuit for its design verification realized in said at least one RFPD the same as one of the state of said at least one roll-back point.  
     
     
         30 . The combined verification method of emulation and simulation according to  claim 27  or  28 , 
 wherein the extended circuit for its design verification added with the additional circuit for IOP-probe is realized in at least one RFPD equipped on the arbitrary prototyping board or arbitrary PCB so as to make the input/probe probe possible;  
 wherein the complete state information or the partial state information is extracted from the extended circuit for its design verification performed on said at least one RFPD whenever at least one output probe is periodically or non-periodically performed during the emulation, temporarily stopping the circuit for its design verification included in the extended circuit for its design verification only during a certain period of time of the output probe process, and then, the extracted information is transmitted to the server computer through the interface module so as to establish at least one roll-back point; simultaneously, the input sequence is sampled in real time per every clock during the emulation when necessary, without stopping the circuit for its design verification, through the output probe of the input signals inside said RFPD, and then, the sampled input sequence is temporarily stored in the embedded memory existing inside said RFPD;  
 wherein the circuit for its design verification is temporarily stopped to read data stored in said embedded memory, and then, the data as read is transmitted to the server computer through very small numbers of at least one output probe line provided in said RFPD via the interface module in order and then stored in the memory so as to replay the emulation; simultaneously, in case where DRAM or SDRAM is used together with RFPD in said arbitrary prototyping board or arbitrary PCB, for specific control signal lines connected to DRAM or SDRAM in RFPD, a specific single value or a transition value is assigned during such transmission process of the probe data so that refresh or auto-refresh of DRAM or SDRAM is made possible and the data loss of DRAM or SDRAM during the transmission process is prevented;  
 wherein during a certain period of time desired by a user after the emulation is completed, the probe of signals for probe, the signals existing in the circuit for its design verification or the HDL code for its design verification, is obtained by performing both the emulation using the input sequence stored in said memory and the simulation using the arbitrary simulator when necessary, through the input probe using said extracted state information as to said at least one RFPD, after making the state of the circuit for its design verification realized in said at least one RFPD the same as the state of said at least one roll-back point.  
 
     
     
         31 . The combined verification method of emulation and simulation according to  claim 27 , wherein the emulation of the circuit for its design verification having a circuit portion needed for a design correction is performed with high speed in at least one RFPD on the arbitrary rapid prototyping board or arbitrary PCB which realizes the entire circuit for its design verification, for which the design correction is not made, as the extended circuit for its design verification added with the additional circuit for IOP-probe, thereafter, the simulation of a partial portion of the circuit for its design verification, the design of the partial portion being corrected by the output probe using the result of such emulation, is performed in the server computer, and the results of said circuit portion which is not corrected in design, being performed by the emulation through the input probe using the result of such simulation, are corrected, thereby enabling the right emulation of the entire circuit for its design verification.  
     
     
         32 . The combined verification method of emulation and simulation according to  claim 30 , wherein in case that a memory existing in a user circuit for its design verification is realized by an on-chip memory in RFPD, for the output probe of the memory existing in said user circuit, the contents of said on-chip memory are copied in real time as a separate probe data storage memory, without temporarily stopping the user clocks or slowing them than the original user clocks by using said separate probe data storage memory, thereafter, the contents stored in the probe data storage memory are read.  
     
     
         33 . The combined verification method of emulation and simulation according to  claim 30 , wherein in case that the memory existing in the user clock for its design verification is embodied by an off-chip memory on the arbitrary prototyping board, for the output probe of the memory existing in said user circuit, the contents of said off-chip memory are copied in real time as a separate probe data storage memory, without temporarily stopping the user clocks or slowing them than the original user clocks by using said separate probe data storage memory, thereafter, the contents stored in the probe data storage memory are read.  
     
     
         34 . The combined verification method of emulation and simulation according to  claim 32  or  33 , wherein for the output probe of the memory existing in the user circuit, a tag is maintained in said separate probe data storage memory, for read/write at a specific address of the user circuit memory the read is performed with either said specific address or the predetermined address in pre-determined order of the user circuit memory at a first period of a system clock, which is two times faster than a user clock, so as to store the read data at the same address in the probe data storage memory and to modify said corresponding tag, and then, the original reading/writing at said specific address in the user circuit memory is performed at the second period of the system clock.