Chip scale package and method of fabricating the same

Abstract

Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.

What is claimed is:  
     
         1 . A chip scale package comprising: 
 a chip having a first surface provided with a first terminal and a second surface provided with a second terminal, the second surface being opposite to the first surface;    a first and a second conductive layers formed on the first and the second surfaces of the chip, respectively; and    electrode surfaces formed on each of designated side surfaces of the first and the second conductive layers.    
     
     
         2 . The chip scale package as set forth in  claim 1 , further comprising passivation layers, each formed on the exposed surfaces of the first and the second conductive layers except for the side surfaces having the electrode surfaces.  
     
     
         3 . The chip scale package as set forth in  claim 2 , wherein said passivation layers are made of insulating films formed by coating insulation resin.  
     
     
         4 . The chip scale package as set forth in  claim 1 , wherein the side surface of the chip and the side surfaces of the first and the second conductive layers form one flat surface.  
     
     
         5 . The chip scale package as set forth in  claim 1 , wherein the conductive layers are metal layers including copper (Cu).  
     
     
         6 . The chip scale package as set forth in  claim 1 , wherein the electrode surfaces are metal layers including gold (Au).  
     
     
         7 . The chip scale package as set forth in  claim 1 , wherein each of the first and the second conductive layers comprises a plating layer formed on the first and the second surfaces of the chip, and at least one copper layer stacked on the plating layer.  
     
     
         8 . The chip scale package as set forth in  claim 1 , wherein the chip is a diode.  
     
     
         9 . A chip scale package assembly comprising: 
 a chip scale package comprising: 
 a chip having a first surface provided with a first terminal and a second surface provided with a second terminal, the second surface being opposite to the first surface;  
 a first and a second conductive layers formed on the first and the second surface of the chip, respectively; and  
 electrode surfaces formed on each of designated side surfaces of the first and the second conductive layers; and  
   a printed circuit board comprising: 
 connection pads for being connected to the electrode surfaces of the chip scale package; and  
 circuit patterns connected to the connection pads.  
   
     
     
         10 . The chip scale package assembly as set forth in  claim 9 , further comprising passivation layers, each formed on the exposed surfaces of the first and the second conductive layers except for the side surfaces having the electrode surfaces.  
     
     
         11 . The chip scale package assembly as set forth in  claim 10 , wherein said passivation layers are made of insulating films formed by coating insulation resin.  
     
     
         12 . The chip scale package assembly as set forth in  claim 9 , wherein the conductive layers are metal layers including copper (Cu).  
     
     
         13 . The chip scale package assembly as set forth in  claim 9 , wherein the electrode surfaces are metal layers including gold (Au).  
     
     
         14 . The chip scale package assembly as set forth in  claim 9 , wherein each of the first and the second conductive layers comprises a plating layer formed on the first and the second surfaces of the chip, and at least one copper layer stacked on the plating layer.  
     
     
         15 . The chip scale package assembly as set forth in  claim 9 , wherein the chip is a diode.  
     
     
         16 . A method of fabricating a chip scale package, said method comprising the steps of: 
 (i) preparing a wafer including a plurality of chips, said chip including a terminal on each of its upper and its lower surfaces, respectively;    (ii) forming conductive layers, each formed on the upper and the lower surfaces of the wafer; and    (iii) dicing the wafer into package units, each package unit including a chip, followed by forming electrode surfaces formed each of designated side surfaces of the conductive layers.    
     
     
         17 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the step (iii) further comprises the step of forming passivation layers, each formed on the exposed surfaces of the first and the second conductive layers except for the side surfaces having the electrode surfaces.  
     
     
         18 . The method of fabricating the chip scale package as set forth in  claim 17 , wherein said passivation layers are made of insulating films formed by coating insulation resin.  
     
     
         19 . The method of fabricating the chip scale package as set forth in  claim 16 , after the step (ii), further comprising the step of forming passivation layers, each formed on the first and the second conductive layers except for the side surfaces having the electrode surfaces, 
 wherein the step (iii) comprises the sub-steps of: 
 first-dicing the wafer so that one side surface of the chip scale package is formed;  
 forming electrode surfaces on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by first-dicing the wafer;  
 second-dicing the wafer into package units; and  
 forming passivation layers on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by second-dicing the wafer.  
   
     
     
         20 . The method of fabricating the chip scale package as set forth in  claim 19 , wherein the step of first-dicing the wafer is the step of dicing the wafer so that scribe lines of the wafer are cut into two rows.  
     
     
         21 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the step (iii) comprises the sub-steps of: 
 first-dicing the wafer so that one side surface of the chip scale package is formed;    forming passivation layers on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by first-dicing the wafer;    second-dicing the wafer into package units; and    forming electrode surfaces on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface obtained by second-dicing the wafer.    
     
     
         22 . The method of fabricating the chip scale package as set forth in  claim 21 , wherein in the step of first-dicing, the wafer is diced into two package units.  
     
     
         23 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the conductive layers are formed by a plating method.  
     
     
         24 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the conductive layers are metal layers including copper (Cu).  
     
     
         25 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the electrode surfaces are metal layers including gold (Au).  
     
     
         26 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the conductive layers are formed by forming metal layers by a plating method and by stacking at least one copper layer on each metal layer.  
     
     
         27 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the electrode surfaces are formed by a plating method.  
     
     
         28 . The method of fabricating the chip scale package as set forth in  claim 16 , wherein the chip is a diode.