Semiconductor device having a capacitor and method for the manufacture thereof

Abstract

A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (Al x O y ) layer.

What is claimed is:  
     
         1 . A semiconductor device for use in a memory cell, comprising: 
 an active matrix provided with a transistor and a first insulating layer formed around the transistor;    a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film;    a second insulating layer formed on top of the transistor and the capacitor structure;    a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and    a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (Al x O y ) layer.    
     
     
         2 . The semiconductor device as recited in  claim 1 , wherein the hydrogen barrier layer is formed to a thickness ranging from approximately 2 nm to 100 nm by using a method selected from the group consisting of an atomic layer deposition (ALD) and a physical vapor deposition (PVD).  
     
     
         3 . The semiconductor device as recited in  claim 1 , wherein the metal interconnection includes a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), aluminum (Al) and combinations thereof.  
     
     
         4 . The semiconductor device of  claim 1 , further comprising: 
 a TiN adhesion layer for connecting the metal interconnection and the top electrode, formed on top of the top electrode;    an inter-metal dielectric (IMD) layer formed on top of the hydrogen barrier layer; and    a passivation layer formed on top of the metal interconnection by using a plasma enhanced CVD in a hydrogen rich ambient.    
     
     
         5 . The semiconductor as recited in  claim 4 , wherein the IMD layer is a triple layer provided with a SiON layer of 100 nm in thickness, a SOG (spin on glass) layer of 400 nm in thickness, and a SRO (silicon rich oxide) layer of 400 nm in thickness.  
     
     
         6 . The semiconductor device as recited in  claim 4 , wherein the passivation layer is a double layer provided with an undoped silicate glass (USG) layer and a Si 3 N 4  layer.  
     
     
         7 . The semiconductor device as recited in  claim 1 , wherein the capacitor thin film includes a material selected from the group consisting of SBT (SrBiTaO x ) and PZT (PbZrTiO x ).  
     
     
         8 . A method for manufacturing a semiconductor device, comprising steps of: 
 a) preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor;    b) forming a capacitor structure on top of the first insulating layer, wherein the capacitor structure includes a capacitor thin film made of a ferroelectric material;    c) forming a second insulating layer on top of the capacitor structure and the transistor;    d) forming a metal interconnection layer and patterning the metal interconnection layer into a predetermined configuration to electrically connect the transistor to the capacitor structure; and    e) forming a hydrogen barrier layer provided with an aluminum oxide (Al x O y ) layer on top of the metal interconnection.    
     
     
         9 . The method as recited in  claim 8 , wherein the hydrogen barrier layer is formed to a thickness ranging from approximately 2 nm to approximately 100 nm by using a method selected from the group consisting of an atomic layer deposition (ALD) and a physical vapor deposition (PVD).  
     
     
         10 . The method as recited in  claim 8 , wherein the metal interconnection includes a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), aluminum (Al) and combinations thereof.  
     
     
         11 . The method as recited in  claim 8 , further comprising steps of: 
 f) forming a TiN adhesion layer on top of the top electrode for connecting the metal interconnection and a top electrode;    g) forming an inter-metal dielectric (IMD) layer on top of the hydrogen barrier layer; and    h) forming a passivation layer on top of the metal interconnection by using a plasma enhanced CVD in a hydrogen rich ambient.    
     
     
         12 . The method as recited in  claim 11 , wherein the IMD layer is a triple layer provided with a SiON layer of 100 nm in thickness, a SOG layer of 400 nm in thickness, and a SRO (silicon rich oxide) layer of 400 nm in thickness.  
     
     
         13 . The method as recited in  claim 11 , wherein the passivation layer is a double layer provided with an undoped silicate glass (USG) layer and a Si 3 N 4  layer.  
     
     
         14 . The method as recited in  claim 11 , wherein the step h) is carried out at a temperature ranging from approximately 320° C. to approximately 400° C.  
     
     
         15 . The method as recited in  claim 8 , wherein the capacitor thin film includes a material selected from the group consisting of SBT (SrBiTaO x ) and PZT (PbZrTiO x ).  
     
     
         16 . The method as recited in  claim 8 , wherein the second insulating layer is a double layer provided with a boron-phosphor-silicate-glass (BPSG) layer and a tetra-ethyl-ortho-silicate (TEOS)-based oxide layer.  
     
     
         17 . The method as recited in  claim 8 , after the step c), further comprising the step of annealing the second insulating layer for densification at a temperature ranging from approximately 500° C. to approximately 900° C. for at least 10 minutes in nitrogen and oxygen ambient.