Multi-die chip and method for making the same

Abstract

The present invention generally relates to a die perimeter region of a die having a microelectromechanical assembly fabricated thereon. This die perimeter region may be configured to facilitate electrically interconnecting adjacent die on a wafer. Moreover, this die perimeter region may be configured to facilitate separating the die from a wafer.

What is claimed:  
     
         1 . A chip, comprising: 
 a substrate;    an oxide layer;    a dielectric layer; and    a plurality of die, wherein each of said plurality of die comprises a die perimeter region and a device region disposed inwardly of said die perimeter region, wherein said device region of each of said plurality of die comprises a first microelectromechanical assembly such that said chip comprises a plurality of said first microelectromechanical assemblies, wherein said oxide layer is disposed between said dielectric layer and said substrate in said device region of each of said plurality of die, and wherein said die perimeter region of each of said plurality of die is devoid of said oxide layer such that said dielectric layer is disposed directly on said substrate in each said die perimeter region.    
     
     
         2 . A chip, as claimed in  claim 1 , wherein: 
 said substrate is formed from a material selected from the group consisting of silicon, gallium arsenide, gallium arsenide phosphide, and ceramics, said oxide layer is formed from a material selected from the group consisting of silicon dioxide and silicon oxynitrides, and said dielectric layer is formed from a material selected from the group consisting of silicon nitride and silicon carbide.    
     
     
         3 . A chip, as claimed in  claim 1 , wherein: 
 said oxide layer is totally encased by said dielectric layer.    
     
     
         4 . A chip, as claimed in  claim 1 , wherein: 
 each adjacent pair of die of said plurality of die are separated by a die boundary, wherein said oxide layer in each said die is spaced back at least about 25 microns back from each surrounding said die boundary.    
     
     
         5 . A chip, as claimed in  claim 1 , wherein: 
 each of said plurality of die are of an identical structure.    
     
     
         6 . A chip, as claimed in  claim 1 , wherein: 
 each said first microelectromechanical assembly comprises a mirror array.    
     
     
         7 . A chip, as claimed in  claim 1 , wherein: 
 each said first microelectromechanical assembly comprises a plurality of mirrors and a plurality of actuators, wherein at least one said actuator is interconnected with each said mirror to control a position of said mirror relative to said substrate.    
     
     
         8 . A chip, as claimed in  claim 1 , wherein: 
 said chip is configured as a device selected from the group consisting of an optical switch, an adaptive optical array, an optical scanner array, and a thermal imaging array.    
     
     
         9 . A chip, as claimed in  claim 1 , wherein: 
 said chip is configured as a device comprising an array of microstructures that encompasses an area greater in size than a single said device region.    
     
     
         10 . A chip, as claimed in  claim 1 , wherein: 
 at least a portion of each said first microelectromechanical assembly is fabricated by surface micromachining.    
     
     
         11 . A chip, as claimed in  claim 1 , wherein: 
 each adjacent pair of die of said plurality of die are separated by a die boundary, wherein each said first microelectromechanical assembly comprises at least one vertically spaced layer, wherein there are no said vertically spaced layers within about 100 microns of any of said die boundaries.    
     
     
         12 . A chip, as claimed in  claim 1 , wherein: 
 said dielectric layer in said die perimeter region of each of said plurality of die is vertically offset from said dielectric layer in said device region of each of said plurality of die.    
     
     
         13 . A chip, as claimed in  claim 1 , wherein: 
 said die perimeter region of each of said plurality of die consists essentially of said substrate, said dielectric layer, and a plurality of electrical traces.    
     
     
         14 . A chip, as claimed in  claim 1 , wherein: 
 said plurality of die comprises first and second die disposed in abutting relation, wherein said chip further comprises:    a first electrical trace disposed in said device region of said first die;    a second electrical trace disposed in said device region of second die;    a third electrical trace extending across adjacent die perimeter regions of said first and second die, wherein said first electrical trace terminates prior to reaching said third electrical trace, and wherein said second electrical trace terminates prior to reaching said third electrical trace.    
     
     
         15 . A chip, as claimed in  claim 14 , wherein: 
 said first and second electrical traces are disposed at a first elevation and said third electrical trace is disposed at a second elevation that is different from said first elevation.    
     
     
         16 . A chip, as claimed in  claim 14 , wherein: 
 said third electrical trace is vertically offset in relation to each of said first and second electrical traces.    
     
     
         17 . A chip, as claimed in  claim 14 , further comprising: 
 a first electrical jump connection between said first and third electrical traces; and    a second electrical jump connection between said second and third electrical traces.    
     
     
         18 . A chip, as claimed in  claim 17 , wherein: 
 said first electrical jump connection comprises a first post interconnected with said first electrical trace, a second post interconnected with said third electrical trace, and a first jumper disposed in vertically spaced relation to an entirety of said dielectric layer and extending between and interconnecting said first and second posts; and    said second electrical jump connection comprises a third post interconnected with said second electrical trace, a fourth post interconnected with said third electrical trace, and a second jumper disposed in vertically spaced relation to an entirety of said dielectric layer and extending between and interconnecting said third and fourth posts.    
     
     
         19 . A chip, as claimed in  claim 17 , wherein: 
 said first and second die are separated by a die boundary, wherein each of said first and second jump connections are spaced from said die boundary by a distance of at least about 25 microns.    
     
     
         20 . A chip, as claimed in  claim 1 , further comprising: 
 a plurality of electrical traces extending between said device regions of each adjacent pair of said plurality of die.    
     
     
         21 . A chip, as claimed in  claim 20 , further comprising: 
 a shield disposed over each of said plurality of electrical traces, wherein each said shield is spaced back at least about 25 microns from a die boundary between each said in adjacent pair of said plurality of die.    
     
     
         22 . A chip, as claimed in  claim 1 , further comprising: 
 a chip perimeter and a chip perimeter region disposed inwardly of said chip perimeter, wherein said dielectric layer is disposed directly on said substrate in said chip perimeter region such that said chip perimeter region is devoid of said oxide layer.    
     
     
         23 . A chip, as claimed in  claim 21 , further comprising: 
 a plurality of electrical traces extending through said chip perimeter region and terminating at said chip perimeter.    
     
     
         24 . A chip, as claimed in  claim 23 , further comprising: 
 a shield disposed over at least a portion of each of said plurality of electrical traces, wherein each said shield is spaced back at least about 25 microns from said chip perimeter.    
     
     
         25 . A chip, comprising: 
 a substrate;    a plurality of die comprising first and second die, wherein each of said plurality of die comprises a die perimeter region and a device region disposed inwardly of said die perimeter region, wherein said device region of each of said plurality of die comprises a first microelectromechanical assembly such that said chip comprises a plurality of said first microelectromehanical assemblies;    a first electrical trace disposed in said device region of said first die;    a second electrical trace disposed in said device region of said second die;    a third electrical trace extending across adjacent die perimeter regions of said first and second die, wherein said first electrical trace terminates prior to reaching said third electrical trace, and wherein said second electrical trace terminates prior to reaching said third electrical trace;    a first electrical jump connection between said first and third electrical traces; and    a second electrical jump connection between said second and third electrical traces.    
     
     
         26 . A chip, as claimed in  claim 25 , wherein: 
 said first and second die are separated by a die boundary, wherein each of said first and second jump connections are spaced from said die boundary by a distance of at least about 25 microns.    
     
     
         27 . A chip, as claimed in  claim 25 , wherein: 
 said first electrical jump connection comprises a first post interconnected with said first electrical trace, a second post interconnected with said third electrical trace, and a first jumper disposed in vertically spaced relation to said first and third electrical traces and extending between and interconnecting said first and second posts; and    said second electrical jump connection comprises a third post interconnected with said second electrical trace, a fourth post interconneced with said third electrical trace, and a second jumper disposed in vertically spaced relation said second and third electrical traces and extending between and interconnecting said third and fourth posts.    
     
     
         28 . A chip, as claimed in  claim 25 , wherein: 
 each of said plurality of die are of an identical structure.    
     
     
         29 . A chip, as claimed in  claim 25 , wherein: 
 each said first microelectromechanical assembly comprises a mirror array.    
     
     
         30 . A chip, as claimed in  claim 25 , wherein: 
 each said first microelectromechanical assembly comprises a plurality of mirrors and a plurality of actuators, wherein at least one said actuator is interconnected with each said mirror to control a position of said mirror relative to said substrate.    
     
     
         31 . A chip, as claimed in  claim 25 , wherein: 
 said chip is configured as a device selected from the group consisting of an optical switch, an adaptive optical array, an optical scanner aray, and a thermal imaging array.    
     
     
         32 . A chip, as claimed in  claim 25 , wherein: 
 at least a portion of each said first microelectromechanical assembly is fabricated by surface micromachining.    
     
     
         33 . A chip, as claimed in  claim 25 , wherein: 
 each adjacent pair of die of said plurality of die are separated by a die boundary, wherein each said first microelectromechanical assembly comprises at least one vertically spaced layer, wherein there are no said vertically spaced layers within about 100 microns of any of said die boundaries.    
     
     
         34 . A chip, as claimed in  claim 25 , wherein: 
 said first and second electrical traces are disposed at a first elevation and said third electrical trace is disposed at a second elevation that is different from said first elevation.    
     
     
         35 . A chip, as claimed in  claim 25 , wherein: 
 said third electrical trace is vertically offset in relation to each of said first and second electrical traces.    
     
     
         36 . A chip, as claimed in  claim 25 , further comprising: 
 an oxide layer;    a dielectric layer, wherein said oxide layer is disposed between said dielectric layer and said substrate in said device region of each of said plurality of die, and wherein said die perimeter region of each of said plurality of die is devoid of said oxide layer such that said dielectric layer is disposed directly on said substrate in each said die perimeter region.    
     
     
         37 . A chip, as claimed in  claim 36 , wherein: 
 said die perimeter region of each of said plurality of die consists essentially of said substrate, said dielectric layer, and a plurality of electrical traces.    
     
     
         38 . A chip, as claimed in  claim 36 , wherein: 
 said substrate is formed from a material selected from the group consisting of silicon, gallium arsenide, gallium arsenide phosphide, and ceramics, said oxide layer is formed from a material selected from the group consisting of silicon dioxide and silicon oxynitrides, and said dielectric layer is formed from a material selected from the group consisting of silicon nitride and silicon carbide.    
     
     
         39 . A chip, as claimed in  claim 36 , wherein: 
 said oxide layer is totally encased by said dielectric layer.    
     
     
         40 . A chip, as claimed in  claim 36 , wherein: 
 each adjacent pair of die of said plurality of die are separated by a die boundary, wherein said oxide layer in each said die is spaced back at least about 25 microns from each surrounding said die boundary.    
     
     
         41 . A chip, as claimed in  claim 36 , wherein: 
 said dielectric layer in said die perimeter region of each of said plurality of die is vertically offset from said dielectric layer in said device region of each of said plurality of die.    
     
     
         42 . A chip, as claimed in  claim 36 , further comprising: 
 a chip perimeter and a chip perimeter region disposed inwardly of said chip perimeter, wherein said dielectric layer is disposed directly on said substrate in said chip perimeter region such that said chip perimeter region is devoid of said oxide layer.    
     
     
         43 . A chip, as claimed in  claim 42 , further comprising: 
 a plurality of electrical traces extending through said chip perimeter region and terminating at said chip perimeter.    
     
     
         44 . A chip, as claimed in  claim 43 , further comprising: 
 a shield disposed over at least a portion of each of said plurality of electrical traces, wherein each said shield is spaced back at least about 25 microns from said chip perimeter.    
     
     
         45 . A method for fabricating a chip, comprising the steps of: 
 forming a first oxide layer over a substrate;    forming a first die boundary channel in said first oxide layer that extends down through said first oxide layer and to said substrate;    forming a dielectric layer over said first oxide layer and within at least a lower portion of said first die boundary channel;    defining first and second die on opposite sides of at least a portion of said first die boundary channel, wherein each said die comprises a microelectromechanical assembly; and    separating said first die from said second die at least along a portion of said first die boundary channel.    
     
     
         46 . A method, as claimed in  claim 45 , wherein said forming a first die boundary channel step comprises patterning said first oxide layer.  
     
     
         47 . A method, as claimed in  claim 45 , wherein said forming a first die boundary channel step comprises defining first and second sidewalls of said first die boundary channel with first and second edge surfaces, respectively, of said first oxide layer.  
     
     
         48 . A method, as claimed in  claim 47 , wherein said first and second edge surfaces of said first oxide layer are separated by a distance within a range of about 50 microns to about 300 microns.  
     
     
         49 . A method, as claimed in  claim 47 , wherein said first and second edge surfaces of said first oxide layer are disposed in at least generally parallel relation.  
     
     
         50 . A method, as claimed in  claim 47 , wherein said forming a dielectric layer step comprises coating said first and second edge surfaces of said first oxide layer with a dielectric material.  
     
     
         51 . A method, as claimed in  claim 45 , wherein said forming a first die boundary channel step comprises defining a closed perimeter for said first die boundary channel, wherein said first die is surrounded by said first die boundary channel.  
     
     
         52 . A method, as claimed in  claim 45 , wherein said forming a dielectric layer step comprises filling only a lower portion of said first die boundary channel with a dielectric material.  
     
     
         53 . A method, as claimed in  claim 45 , wherein said forming a dielectric layer step comprises protecting said first oxide layer from exposure to a release etchant to which said chip is exposed after said separating step.  
     
     
         54 . A method, as claimed in  claim 45 , wherein said defining first and second die step comprises using a field stepper.  
     
     
         55 . A method, as claimed in  claim 45 , wherein: 
 said defining first and second die step comprises forming an identical said microelectromechanical assembly on each of said first and second die.    
     
     
         56 . A method, as claimed in  claim 55 , wherein said defining first and second die step comprises forming all microstructures of said microelectromechanical assembly for each of said first and second die outside of said first die boundary channel.  
     
     
         57 . A method, as claimed in  claim 45 , wherein said separating step comprises sawing at least generally along said at least a portion of said first die boundary channel.  
     
     
         58 . A method, as claimed in  claim 45 , wherein said defining first and second die step comprises forming at least one electrical trace that extends across said at least a portion of said first die boundary channel directly on said dielectric layer.  
     
     
         59 . A method, as claimed in  claim 58 , further comprising the step of forming a shield over only a portion of each said electrical trace such that said separating step fails to pass through any portion of any said shield.  
     
     
         60 . A method, as claimed in  claim 59 , wherein said separating step defines a first edge of said chip, wherein each said shield is separated from said first edge by a distance of at least about 25 microns.  
     
     
         61 . A method, as claimed in  claim 45 , wherein said defining first and second die step comprises forming a first electrical trace for said first die that is located out of said first die boundary channel, forming a second electrical trace for said second die that is located out of said first die boundary channel, forming a third electrical trace on said dielectric layer within said first die boundary channel, forming a first jump connection between said first and third electrical traces, and forming a second jump connection between said second and third electrical traces.  
     
     
         62 . A method, as claimed in  claim 61 , wherein a first portion of said third electrical trace is associated with said first die and a second portion of said third electrical trace is associated with said second die, and wherein ends of said first and second portions of said third electrical trace are merged together.  
     
     
         63 . A method, as claimed in  claim 61 , wherein said forming a dielectric layer step comprises forming a second die boundary channel within said first die boundary channel, wherein said second die boundary channel comprises a base and first and second sidewalls that are defined by a dielectric material, wherein said third electrical trace terminates prior to reaching said first sidewall of said second die boundary channel and prior to reaching said second sidewall of said second die boundary channel.  
     
     
         64 . A method for fabricating a chip, comprising the steps of: 
 forming a plurality of rows and columns of die on a wafer, wherein each of said die is identical and comprises a first microelectromechanical assembly; and    electrically interconnecting at least one of each adjacent pair of said die in each of said columns and each said adjacent pair of said die in each of said rows such that a first chip of a first number of said die may be formed from said wafer and that a second chip of a second number of said die may be formed from said wafer, wherein said first number is different from said second number.    
     
     
         65 . A chip, comprising: 
 a substrate;    a plurality of die comprising first and second die, wherein each said die comprises a first microelectromechanical assembly such that said chip comprises a plurality of said first microelectromechanical assemblies;    a die boundary between each adjacent pair of said die and comprising a first die boundary between said first and second die;    a first electrical trace extending from said first die boundary at least toward said first microelectromechanical assembly of said first die;    a first shield that is spaced from said first die boundary by a distance of at least about 25 microns and that is then disposed over a corresponding portion of said first electrical trace;    a second electrical trace extending from said first die boundary at least toward said first microelectromechanical assembly of said second die; and    a second shield that is spaced from said first die boundary by a distance of at least about 25 microns and that is then disposed over a corresponding portion of said second electrical trace.