Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

Abstract

A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.

What is claimed is:  
     
         1 . A silicon-on-insulator metal oxide semiconductor device which is radiation hardened, comprising: 
 an ultrathin silicon-on-sapphire substrate; and    at least one P-channel MOS transistor fabricated in the ultrathin silicon layer, wherein the ultrathin silicon layer in the P-channel region of the transistor is characterized by a retrograde N-type dopant concentration profile.    
     
     
         2 . A device according to  claim 1 , wherein in the P-channel region the N-type dopant concentration is at least twice as high near the silicon-insulator interface as near the top of the silicon layer.  
     
     
         3 . A device according to  claim 1 , wherein the N-type dopant concentration is at least ten times as high near the silicon-insulator interface as near the top of the silicon layer.  
     
     
         4 . A device according to  claim 1 , wherein the N-type dopant is selected from the group consisting of phosphorus, arsenic and antimony.  
     
     
         5 . A device according to  claim 1 , further comprising an N-channel MOS transistor fabricated on said ultrathin silicon-on-sapphire substrate, thereby forming a CMOS device.  
     
     
         6 . A method for making a silicon-on-insulator metal oxide semiconductor device which is radiation hardened, comprising the steps of: 
 providing an ultrathin silicon-on-sapphire substrate;    forming a retrograde N-type dopant concentration profile in a region of the ultrathin silicon layer; and    forming a P-channel MOS transistor in the ultrathin silicon layer, wherein at least a portion of the N-type retrograde dopant concentration profile region forms the P-channel region of the P-channel MOS transistor.    
     
     
         7 . A method according to  claim 6 , wherein the N-type dopant is selected from the group consisting of phosphorus, arsenic and antimony.  
     
     
         8 . A method according to  claim 6 , wherein the retrograde N-type dopant concentration profile is produced by ion implantation.  
     
     
         9 . A method according to  claim 8 , wherein the retrograde ion implant step is performed at an energy in the range of 100 to 200 Kev.  
     
     
         10 . A method according to  claim 6 , wherein the retrograde N-type dopant concentration profile is produced by epitaxy.  
     
     
         11 . A method according to  claim 6 , further comprising the steps of forming an N-channel MOS transistor in said ultrathin silicon-on-sapphire substrate so as to produce a CMOS active device.  
     
     
         12 . A method according to  claim 11  wherein said steps of forming a retrograde N-type dopant concentration profile, forming a P-channel MOS transistor, and forming an N-channel MOS transistor are performed at a temperature less than approximately 950° degrees celsius.