Anti-spacer structure for improved gate activation

Abstract

A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film. The inventive structure contains a non-conformal film formed on both horizontal and vertical surfaces of a structure including at least non-predoped patterned gate regions.

Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is:  
     
         1 . A method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) device comprising the steps of: 
 (a) forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material;    (b) forming a non-conformal film on said structure including at least said plurality of patterned gate stacks;    (c) blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked;    (d) implanting first ions into said unblocked patterned gate stacks;    (e) removing said first resist and blocking said previously unblocked patterned gate stacks with a second resist;    (f) implanting second ions into said patterned gate stacks that are not blocked by said second resist; and    (g) removing said second resist and said non-conformal film.    
     
     
         2 . The method of  claim 1  wherein step (a) comprising the steps of: forming at least one gate material on said gate dielectric and patterning said gate material via lithography and etching.  
     
     
         3 . The method of  claim 2  wherein said at least one gate material comprises a conductive material or a material that can be made conductive.  
     
     
         4 . The method of  claim 2  wherein said at least one gate material is selected from the group consisting of polysilicon, amorphous silicon, an elemental metal or alloys thereof, a silicide or nitride of an elemental metal and any combination thereof.  
     
     
         5 . The method of  claim 4  wherein said elemental metal is W, Pt, Pd, Ru, Rh or Ir.  
     
     
         6 . The method of  claim 2  wherein said at least one gate material is comprised of polysilicon or amorphous silicon.  
     
     
         7 . The method of  claim 1  wherein said non-conformal film is formed by a non-conformal deposition process, a non-conformal deposition process and isotropic etching, or a conformal deposition process and lateral etching.  
     
     
         8 . The method of  claim 1  wherein said non-conformal film is thicker over horizontal surfaces as compared with vertical surfaces.  
     
     
         9 . The method of  claim 1  wherein said non-conformal film is comprised of an organic film, an oxide, a nitride or an oxynitride.  
     
     
         10 . The method of  claim 1  wherein said first resist is formed via lithography.  
     
     
         11 . The method of  claim 1  wherein said first ions are comprised of a N-type dopant.  
     
     
         12 . The method of claim I wherein step (d) is performed utilizing an angled ion implantation process.  
     
     
         13 . The method of claim l wherein step (d) is performed utilizing an ion dose of about 5E15 cm −2  or greater.  
     
     
         14 . The method of  claim 1  wherein said second resist is formed via lithography.  
     
     
         15 . The method of  claim 1  wherein said second ions are comprised of a P-type dopant.  
     
     
         16 . The method of  claim 1  wherein step (f) is performed utilizing an angled ion implantation process.  
     
     
         17 . The method of claim I wherein step (f) is performed utilizing an ion dose of about 5E15 cm −2  or greater.  
     
     
         18 . The method of  claim 1  wherein source/drain extension regions and source/drain diffusion regions are formed in a surface of a semiconductor substrate which is present beneath said gate dielectric prior to performing step (b).  
     
     
         19 . The method of  claim 1  wherein source/drain extension regions and source/drain diffusion regions are formed in a surface of a semiconductor substrate which is present beneath said gate dielectric following implant steps (d) and (f).  
     
     
         20 . The method of  claim 1  wherein source/drain extension regions and source/drain diffusion regions are formed in a surface of a semiconductor substrate that is present beneath said gate dielectric after performing step (g).  
     
     
         21 . The method of claim I wherein said implanted patterned gate stacks are activated after steps (d) or (e) using separate activation annealing steps.  
     
     
         22 . The method of  claim 1  wherein said implanted patterned gate stacks are activated using a single activation annealing step after said removal of said second resist or after said removal of said non-conformal film.  
     
     
         23 . An anti-spacer structure comprising: a semiconductor substrate having a layer of gate dielectric material formed on a surface thereof; 
 a plurality of patterned gate regions formed on said layer of gate dielectric material, said plurality of patterned gate regions not being pre-doped; and    a non-conformal film formed atop said layer of gate dielectric and said plurality of patterned gate regions, wherein said non-conformal film is thicker over horizontal surfaces, while being thinner or non-existent over vertical sidewalls of each of said patterned gate regions.    
     
     
         24 . The anti-spacer structure of  claim 23  wherein said semiconductor substrate is comprised of a semiconducting material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP, Si/Si, Si/SiGe and silicon-on-insulators.  
     
     
         25 . The anti-spacer structure of  claim 23  wherein said gate dielectric is comprised of an oxide, a nitride, an oxynitride or any combinations and multilayers thereof.  
     
     
         26 . The anti-spacer structure of  claim 25  wherein said gate dielectric is comprised of an oxide selected from the group consisting of SiO 2 , ZrO 2 , Ta 2 O 5 , HfO 2  and A 1   2 O 3 .  
     
     
         27 . The anti-spacer structure of  claim 23  wherein said patterned gate stack region comprises at least one gate material.  
     
     
         28 . The anti-spacer structure of  claim 27  wherein said at least one gate material comprises a conductive material or a material that can be made conductive.  
     
     
         29 . The anti-spacer structure of  claim 27  wherein said at least one gate material is selected from the group consisting of polysilicon, amorphous silicon, an elemental metal or alloy thereof, a silicide or nitride of an elemental metal and any combination thereof.  
     
     
         30 . The anti-spacer structure of  claim 29  wherein said elemental metal is W, Pt, Pd, Ru, Rh or Ir.  
     
     
         31 . The anti-spacer structure of  claim 27  wherein said at least one gate material is comprised of polysilicon or amorphous silicon.  
     
     
         32 . The anti-spacer structure of  claim 23  wherein said non-conformal film is comprised of an organic film, an oxide, a nitride or an oxynitride.  
     
     
         33 . The anti-spacer structure of  claim 23  wherein said layer of gate dielectric is patterned and said plurality of patterned gate regions are formed on said patterned gate dielectric and said non-conformal film is formed on exposed surfaces of said substrate as well as patterned regions formed thereon.