Semiconductor memory device, refresh control method thereof, and test method thereof

Abstract

The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

What is claimed is:  
     
         1 . A semiconductor memory device for sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations, comprising: 
 a designator section for designating a corresponding address group related to a word line group to be intended for the refresh operation according to a plurality of the refresh request signals;    a storage section for storing in advance a predetermined address group related to a predetermined word line group including word lines connected with memory cells having predetermined data-holding characteristics;    a comparator section for comparing the corresponding address group designated by the designator section and the predetermined address group stored in the storage section; and    a judgment section for judging whether the refresh operation is executable, according to the result of comparison by the comparator section.    
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein the designator section includes a dedicated decoder different from a row address decoder for decoding a corresponding address related to each word line intended for the refresh operation.  
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein the designator section includes a row address decoder for decoding a corresponding address related to each word line intended for the refresh operation.  
     
     
         4 . A semiconductor memory device for sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations, comprising: 
 a refresh-thinning-out controller section including a designator section for designating a corresponding address related to a word line intended for the refresh operation according to each of the refresh request signals, and a judgment section for comparing the corresponding address and a predetermined address related to a predetermined word line connected with one of memory cells each having predetermined data-holding characteristics and judging whether the refresh operation is executable, according to the result of comparison; and    a switching section for switching an active state of the refresh-thinning-out controller section under predetermined conditions;    wherein when the refresh-thinning-out controller section is defunctionalized, the switching section deactivates at least either one of the designator section or the judgment section.    
     
     
         5 . The semiconductor memory device according to  claim 4 , wherein the switching section includes a timer section for timing a predetermined time, and the active state of the refresh-thinning-out controller section is switched for each predetermined time.  
     
     
         6 . The semiconductor memory device according to  claim 5 , wherein the timer section includes a counter section for counting the number of occurrences of the refresh request signals.  
     
     
         7 . A semiconductor memory device for sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations, comprising: 
 a storage section for storing each of predetermined addresses each compared with a corresponding address related to each word line intended for the refresh operation;    a storage switching section for switching the predetermined addresses to be stored in the storage section between addresses at which memory cells each having first data-holding characteristics are included, and addresses at which memory cells each having second data-holding characteristics are included, according to a distribution of data-holding characteristics included in memory cells; and    a judgment section for switching the result of judgment as to execution/non-execution of the refresh operation according to the switching of the storage switching section.    
     
     
         8 . The semiconductor memory device according to  claim 7 , wherein the first data-holding characteristics are data-holding characteristics same as or better than predetermined data-holding characteristics, and the second data-holding characteristics are data-holding characteristics same as or poorer than predetermined data-holding characteristics, and 
 the judgment section reverses the result of judgment as to the execution/non-execution of the refresh operation between the predetermined addresses at which memory cells each having the first or second data-holding characteristics are included.    
     
     
         9 . A semiconductor memory device for sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations, comprising: 
 a refresh-thinning-out controller section for comparing a corresponding address related to each of the target word lines and each of predetermined addresses related to predetermined word lines connected with memory cells each having predetermined data-holding characteristics and judging whether the refresh operation is executable, according to the result of comparison; and    an output section activated upon testing and for outputting the result of judgment from the refresh-thinning-out controller section to the outside.    
     
     
         10 . The semiconductor memory device according to  claim 9 , further including a buffer section for propagating the result of judgment to the output section upon the testing.  
     
     
         11 . The semiconductor memory device according to  claim 9 , further including an address changer section for switching each of addresses inputted to the refresh-thinning-out controller section to a test address inputted from outside as an alternative to the corresponding address upon the testing.  
     
     
         12 . A semiconductor memory device for sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations, comprising: 
 a refresh-thinning-out controller section for comparing each of corresponding addresses related to each of the target word lines and each of predetermined addresses related to predetermined word lines connected with memory cells each having predetermined data-holding characteristics and judging whether the refresh operation is executable, according to the result of comparison; and    redundant memory cells for relieving defective memory cells;    wherein of the corresponding addresses, redundant addresses in which redundancy setting for the redundant memory cells has been performed, are not judged by the refresh-thinning-out controller section.    
     
     
         13 . The semiconductor memory device according to  claim 12 , wherein the redundancy setting is performed with a predetermined number of word lines including the redundant memory cells being as basic units of redundant regions, and the basic units of the redundant regions are not judged by the refresh-thinning-out controller section.  
     
     
         14 . The semiconductor memory device according to  claim 13 , wherein each of the redundant regions is column redundancy.  
     
     
         15 . The semiconductor memory device according to  claim 12 , wherein the refresh-thinning-out controller section includes a storage section for storing in advance predetermined addresses related to predetermined word lines connected with memory cells each having predetermined data-holding characteristics, and 
 the storage section further stores the redundant addresses therein.    
     
     
         16 . The semiconductor memory device according to  claim 12 , further including a redundancy judgment section for judging whether each of the corresponding addresses is each of the redundant addresses, wherein 
 the refresh-thinning-out controller section has a judgment section for determining whether the refresh operation is executable on each of the corresponding addresses, and    the judgment section is controlled based on the redundancy judgment made by the redundancy judgment section.    
     
     
         17 . A semiconductor memory device wherein an external access operation executed based on each of external-access request signals and a refresh operation executed based on each of refresh request signals produced automatically thereinside are executed independently of each other, comprising: 
 an arbiter section for making arbitration to the external-access request signal and the refresh request signal;    a controller section for controlling decode processing of each corresponding address with respect to either the external access operation or the refresh operation determined by the arbiter section;    a word line driver section for driving a row address decoder for the corresponding address, which is started up by the controller section, and each word line selected by the row address decoder; and    a refresh-thinning-out controller section for making a decision as to execution/non-execution of the refresh operation with respect to the corresponding address outputted according to the refresh request signal;    wherein the row address decoder or the word line driver section is activated and controlled based on the result of determination by the refresh-thinning-out controller section.    
     
     
         18 . A semiconductor memory device wherein an external access operation executed based on each of external-access request signals and a refresh operation executed based on each of refresh request signals produced automatically thereinside are executed independently of each other, comprising: 
 an arbiter section for making arbitration to the external-access request signal and the refresh request signal;    a refresh request section for outputting the refresh request signal to the arbiter section; and    a refresh-thinning-out controller section for making judgment as to execution/non-execution of the refresh operation with respect to a corresponding address outputted according to the refresh request signal;    wherein the refresh request section is controlled based on the result of judgment by the refresh-thinning-out controller section.    
     
     
         19 . A refresh control method of a semiconductor memory device comprising: 
 a step of sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations; and    a step of judging whether the refresh operation is executable, according to data-holding characteristics stored in memory cells connected to a word line group, for each corresponding address group related to the word line group to be intended for the refresh operation in response to a plurality of the refresh request signals.    
     
     
         20 . The refresh control method according to  claim 19 , wherein the corresponding address group is designated by a corresponding decode address obtained by decoding the corresponding address related to each target word line according to the refresh operation, and 
 the corresponding decode address and predetermined decode addresses stored in advance inclusive of word lines connected with memory cells each having predetermined data-holding characteristics are compared to thereby discriminate whether the refresh operation is executable.    
     
     
         21 . A refresh control method of a semiconductor memory device comprising: 
 a step of sequentially selecting target word lines according to refresh request signals to thereby perform refresh operations; and    a step of avoiding judgment as to execution/non-execution of the refresh operation with respect to redundant addresses subject to redundancy setting, of corresponding addresses related to the target word lines.    
     
     
         22 . The refresh control method according to  claim 21 , wherein the redundancy setting is performed with a predetermined number of word lines including redundant memory cells being as basic units of redundant regions, and the basic units of the redundant regions are not judged by the refresh-thinning-out controller section.  
     
     
         23 . The refresh control method according to  claim 22 , wherein the redundancy setting is column redundancy.  
     
     
         24 . The refresh control method according to  claim 21 , wherein the redundant addresses are stored in advance together with predetermined addresses related to predetermined word lines connected with memory cells each having predetermined data-holding characteristics.  
     
     
         25 . A refresh control method of a semiconductor memory device comprising: 
 a step of executing an external access operation based on each of external-access request signals and a refresh operation based on each of refresh request signals produced automatically thereinside, the external operation and the refresh operation being executed independently of each other;    a step of selecting the refresh operation according to arbitaration to the external-access request signal and the refresh request signal and performing a judgment process as to execution/non-execution of the refresh operation relative to the corresponding address in parallel with a word line driving process made following a decode process of the corresponding address intended for the refresh operation; and    a step of activating and controlling the decode process or the word line driving process, based on the result of judgment as to the execution/non-execution thereof.    
     
     
         26 . A refresh control method of a semiconductor memory device comprising: 
 an execution step for executing an external access operation based on each of external-access request signals and a refresh operation based on each of refresh request signals produced automatically thereinside, the external operation and the refresh operation being executed independently of each other;    an access-operation arbitration step for making arbitration to the external-access request signal and the refresh request signal;    a control step for controlling a decode process of each corresponding address with respect to either the external access operation or the refresh operation determined by the access-operation arbitration step;    a row address decode step started up by the control step and for decoding the corresponding address;    a word line driving step executed following the row address decode step; and    a refresh-thinning-out control step for making judgment as to execution/non-execution of the refresh operation relative to the corresponding address in parallel with the processes from the access-operation arbitration step to the word line driving step;    whereby the row address decode step or the word line driving step is activated and controlled based on the result of judgment by the refresh-thinning-out control step.    
     
     
         27 . A refresh control method of a semiconductor memory device comprising: 
 a step of executing an external access operation based on each of external-access request signals and a refresh operation based on each of refresh request signals produced automatically thereinside, the external operation and the refresh operation being executed independently of each other;    a step of judging whether the refresh operation is executable, with respect to each corresponding address outputted according to the refresh request signal; and    a step of arbitrating the refresh request signal and the external-access request signal based on the result of judgment.    
     
     
         28 . A refresh control method of a semiconductor memory device comprising: 
 an execution step for executing an external access operation based on each of external-access request signals and a refresh operation based on each of refresh request signals produced automatically thereinside, the external operation and the refresh operation being executed independently of each other;    a refresh-thinning-out control step for effecting judgment as to execution/non-execution of the refresh operation on each corresponding address outputted according to the refresh request signal;    a refresh request step for allowing the refresh request signal to be effective based on the result of judgment by the refresh-thinning-out control step; and    an access-operation arbitration step for making arbitration to the external-access request signal and the refresh request signal rendered effective.    
     
     
         29 . A test method of a semiconductor memory device, for performing refresh operations according to judgment as to execution/non-execution of the refresh operations every refresh request signals while performing redundancy setting, comprising: 
 a redundant address acquiring step for acquiring each redundant address to be subjected to the redundancy setting;    a predetermined address acquiring step for acquiring predetermined addresses related to memory cells each having predetermined data-holding characteristics; and    a storing step for storing the redundant addresses and the predetermined addresses in the semiconductor memory device in advance to exclude the two from an object for the judgment as to the execution/non-execution of the refresh operation.