Semiconductor memory device and multi-chip module comprising the semiconductor memory device

Abstract

In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.

What is claimed is:  
     
         1 . A semiconductor memory device formed of a semiconductor chip and overlaid onto a surface of another semiconductor chip to be electrically connected therewith, comprising: 
 a memory cell array having a plurality of memory cells; and    a control circuit for controlling reading and writing from and into the memory cells in the memory cell array;    wherein the memory cell array has a predetermined capacity that is selected from a plurality of capacities that are variably set; and    wherein the control circuit is provided with a chip connector portion having terminals for connection with the other semiconductor chip, and the chip connector portion has an invariable configuration regardless of the size of the capacity of the memory cell array.    
     
     
         2 . A semiconductor memory device formed of a semiconductor chip and overlaid onto a surface of another semiconductor, chip to be electrically connected therewith, comprising: 
 a memory cell array having a plurality of memory cells; and    a control circuit for controlling reading and writing from and into the memory cells in the memory cell array;    wherein the memory cell array has a predetermined capacity that is selected from a plurality of capacities that are variably set; and    wherein the control circuit is provided with a chip connector portion having terminals for connection with the other semiconductor chip, and each of the control circuit and the chip connector portion has an invariable configuration regardless of the size of the capacity of the memory cell array.    
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein the chip connector portion includes an operation specification-regulating terminal for regulating an operating specification of the semiconductor memory device.  
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein the chip connector portion includes a generated voltage-regulating terminal for regulating a generated voltage of a voltage generator.  
     
     
         5 . A semiconductor memory device formed of a semiconductor chip and overlaid onto a surface of another semiconductor chip to be electrically connected therewith, comprising: 
 a memory cell array having a plurality of memory cells; and    a control circuit for controlling reading and writing from and into the memory cells in the memory cell array;    wherein the memory cell array comprises a chip connector portion having terminals for overlaying with the other semiconductor ship, and the memory cell array is formed into a plurality of modules each having a predetermined basic capacity; and    wherein the chip connector portion is individually provided for each of the basic capacity units, and all the individually-provided chip connector portions have the same configuration.    
     
     
         6 . The semiconductor memory device according to  claim 5 , wherein each of the individually provided chip connector portions includes an activation controlling terminal that controls, when a refresh operation for restoring memory cell data is performed for memory cells in a basic capacity, whether the memory cells in the basic capacity are activated or are not activated.  
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein the refresh operation is an auto-refresh operation controlled by an external clock and a control terminal.  
     
     
         8 . The semiconductor memory device according to  claim 6 , wherein the refresh operation is a self-refresh operation controlled by an internal clock generated internally.  
     
     
         9 . The semiconductor memory device according to  claim 5 , wherein: 
 the memory cell array comprises a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells; and    each of the individually-provided chip connector portions comprises an all-of the-word-lines-activating terminal for activating all the plurality of word lines in a corresponding basic capacity when in a first electrical state.    
     
     
         10 . The semiconductor memory device according to  claim 5 , wherein: 
 the memory cell array comprises a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells; and    each of the individually-provided chip connector portions comprises a half-of-the-word-lines-activating terminal for selectively activating about half of the plurality of word lines in a corresponding basic capacity according to an address signal when in a first electrical state.    
     
     
         11 . The semiconductor memory device according to  claim 5 , wherein a ground wire is disposed in the same wiring layer in which the terminals of the chip connector portion is formed, the ground wire covering most of the memory cells in the corresponding basic capacity.  
     
     
         12 . A multi-chip module comprising: 
 a slave chip that is the semiconductor memory device according to  claim 1;  and    a master chip having a chip connector portion in which terminals to be connected to the slave chip are formed;    wherein the terminals of the chip connector portion of the slave chip are overlaid onto the terminals of the chip connector portion of the master chip to electrically connect the terminals of the respective chips together.    
     
     
         13 . A multi-chip module comprising: 
 a slave chip that is the semiconductor memory device according to  claim 2;  and    a master chip having a chip connector portion in which terminals to be connected to the slave chip are formed;    wherein the terminals of the chip connector portion of the slave chip are overlaid onto the terminals of the chip connector portion of the master chip to electrically connect the terminals of the respective chips together.    
     
     
         14 . A multi-chip module comprising: 
 a slave chip that is the semiconductor memory device according to  claim 5;  and    a master chip having a chip connector portion in which terminals to be connected to the slave chip are formed;    wherein the terminals of the chip connector portion of the slave chip are overlaid onto the terminals of the chip connector portion of the master chip to electrically connect the terminals of the respective chips together.