Semiconductor device

Abstract

The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

We claim:  
     
         1 . A semiconductor device, comprising: 
 a CMOS circuit having a plurality of MOSFETs having respective threshold voltages less than or equal to 0.5 V;    well voltage applying means for applying a well voltage to the well of each of the plurality of MOSFETs of the CMOS circuit; and    supply voltage applying means for applying a supply voltage to the CMOS circuit;    wherein the supply voltage applying means begins to apply the supply voltage after the well voltage applying means begins to apply the well voltage.    
     
     
         2 . A semiconductor device as claimed in  claim 1 , wherein the threshold voltages of the plurality of MOSFETs of the CMOS circuit are less than or equal to 0.35 V.  
     
     
         3 . A semiconductor device, comprising: 
 a CMOS circuit having a plurality of MOSFETs having respective threshold voltages less than or equal to 0.5 V;    a voltage conversion circuit arranged to receive a first voltage as a supply voltage and to output a second voltage derived from said first voltage as a well voltage to the well of each of the plurality of MOSFETs of the CMOS circuit; and    supply voltage applying means for applying a third voltage as a supply voltage to the CMOS circuit;    wherein the supply voltage applying means begins to apply the third voltage to the CMOS circuit after the voltage conversion circuit receives the first voltage.    
     
     
         4 . A semiconductor device as claimed in  claim 3 , wherein said voltage conversion circuit and said CMOS circuit are contained on the same chip, and wherein the first voltage is greater than the third voltage.  
     
     
         5 . A semiconductor device as claimed in  claim 4 , further comprising a circuit block including said voltage conversion circuit, wherein said circuit block comprises MOSFETs having respective threshold voltages that are greater than the threshold voltages of the MOSFETs in said CMOS circuit.  
     
     
         6 . A semiconductor device as claimed in  claim 5 , wherein said circuit block includes a chip-to-chip input-output interface circuit.  
     
     
         7 . A semiconductor device as claimed in  claim 4 , further comprising a circuit block including said voltage conversion circuit, wherein said circuit block includes a chip-to-chip input-output interface circuit.  
     
     
         8 . A semiconductor device as claimed in  claim 3 , further comprising a circuit block including said voltage conversion circuit, wherein said circuit block comprises MOSFETs having respective threshold voltages that are greater than the threshold voltages of the MOSFETs in said CMOS circuit.  
     
     
         9 . A semiconductor device as claimed in  claim 3 , further comprising a circuit block including said voltage conversion circuit, wherein said circuit block includes a chip-to-chip input-output interface circuit.  
     
     
         10 . A semiconductor device as claimed in  claim 3 , wherein the third voltage is 2 V or lower.  
     
     
         11 . A semiconductor device as claimed in  claim 3 , wherein after the voltage conversion circuit begins to apply the well voltage to the CMOS circuit, the supply voltage applying means begins to apply the third voltage to the CMOS circuit.  
     
     
         12 . A semiconductor device, comprising: 
 a circuit for fixing the well potential of a CMOS circuit having a plurality of MOSFETs having respective threshold voltages less than or equal to 0.5 V; and    a circuit for varying the well potential of said plurality of MOSFETs by capacitive coupling according to the variation of an input signal of said CMOS circuit.    
     
     
         13 . A semiconductor device as claimed in  claim 12 , further comprising a circuit for refreshing the well potential of said MOSFETs when said MOSFETs are in a floating state, to a potential in the direction of cut off of the MOSFETs.  
     
     
         14 . A semiconductor device, comprising: 
 a dynamic memory cell having one MOSFET and a capacitor; and    a CMOS circuit having a plurality of MOSFETs having respective threshold voltages less than or equal to 0.5 V;    wherein the well potential of the MOSFETs constituting said CMOS circuit is subjected to a pulse variation; and    wherein the substrate voltage of said dynamic memory cell is substantially a DC supply voltage.    
     
     
         15 . A semiconductor device, comprising: 
 a static memory cell which is operated with a first operating voltage, said static memory cell including a plurality of MOSFETs of a first threshold voltage; and    a CMOS circuit which is operated with a second operating voltage that is lower than said first operating voltage, said CMOS circuit including a plurality of MOSFETs of a second threshold voltage that is lower than said first threshold voltage;    wherein the well potential of the MOSFETs in said CMOS circuit are subjected to pulse variation.    
     
     
         16 . A semiconductor device, comprising: 
 a CMOS circuit;    a standby control circuit;    a voltage conversion circuit;    wherein an output voltage generated by said voltage conversion circuit is supplied to said standby control circuit, and wherein said standby control circuit varies the well potential of said CMOS circuit using said output voltage, depending on an operating condition of said semiconductor device; and    a capacitor having a capacitance that is greater than the capacitance of said well, said capacitor being connected to the output of said voltage conversion circuit.    
     
     
         17 . A method of operating a semiconductor device, comprising the following steps: 
 applying a well voltage to the well of a plurality of MOSFETs of a CMOS circuit, said plurality of MOSFETs having respective threshold voltages less than or equal to 0.5 V; and    applying a supply voltage to the CMOS circuit after the well voltage applying means begins to apply the well voltage.    
     
     
         18 . A method of operating a semiconductor device as claimed in  claim 17 , wherein the threshold voltages of the plurality of MOSFETs of the CMOS circuit are less than or equal to 0.35 V.  
     
     
         19 . A method of operating a semiconductor device, comprising the following steps: 
 inputting a first voltage to a voltage conversion circuit, and outputting therefrom a second voltage derived from said first voltage to the well of a plurality of MOSFETs of a CMOS circuit, wherein the plurality of MOSFETs have respective threshold voltages less than or equal to 0.5 V; and    applying a third voltage as a supply voltage to the CMOS circuit;    wherein the step of applying the third voltage to the CMOS circuit is begun after the first voltage is input to the voltage conversion circuit.    
     
     
         20 . A method of operating a semiconductor device as claimed in  claim 19 , wherein the first voltage is greater than the third voltage.  
     
     
         21 . A method of operating a semiconductor device as claimed in  claim 19 , wherein the supply voltage applied to the CMOS circuit is 2 V or lower.  
     
     
         22 . A method of operating a semiconductor device as claimed in  claim 19 , wherein wherein the step of applying the third voltage to the CMOS circuit is begun after the outputting step begins to apply the second voltage to the well of the plurality of MOSFETs of the CMOS circuit.  
     
     
         23 . A method of operating a semiconductor device, comprising the following steps: 
 fixing the well potential of a CMOS circuit having a plurality of MOSFETs having respective threshold voltages less than or equal to 0.5 V; and    varying the well potential of said plurality of MOSFETs by capacitive coupling according to the variation of an input signal of said CMOS circuit.    
     
     
         24 . A method of operating a semiconductor device as claimed in  claim 23 , further comprising the step of refreshing the well potential of said MOSFETs when said MOSFETs are in a floating state, to a potential in the direction of cut off of the MOSFETs.  
     
     
         25 . A method of operating a semiconductor device, comprising the following steps: 
 supplying an output voltage from a voltage conversion circuit to a standby control circuit; and    outputting the output voltage from the standby control circuit to a CMOS circuit, to vary the well potential of the CMOS circuit using said output voltage, depending on an operating condition of said semiconductor device;    wherein a capacitor having a capacitance that is greater than the capacitance of said well is connected to the output of said voltage conversion circuit.