Semiconductor device, method for designing the same and recording medium that can be read by computer in which program for designing semiconductor device is recorded

Abstract

A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and is connected to the second internal circuit, at least one first connecting member for connecting between the second semiconductor chip provided on the first semiconductor chip, at least one first conductive pad and at least one second conductive pad, and at least one second connecting member led from at least one first conductive.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to said first internal circuit;    a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and connected to said second internal circuit;    at least one first connecting member for connecting said at least one first conductive pad to said at least one second conductive pad; and    at least one second connecting member led from said at least one first conductive pad.    
     
     
         2 . The semiconductor device of  claim 1 , wherein said at least one first connecting member contacts the point on said at least one first conductive pad which is different from the point said at least one second connecting member contacts.  
     
     
         3 . The semiconductor device of  claim 1 , wherein a plurality of said at least one first conductive pads are provided, 
 a plurality of said at least one second conductive pads are provided,    a plurality of said at least one first connecting member are provided,    a plurality of said at least one second connecting member are provided, and    two of said plurality of first connecting members have the same length.    
     
     
         4 . A semiconductor device comprising: 
 a first semiconductor chip that includes a plurality of first conductive pads provided on its upper surface;    a second semiconductor chip that is provided on said first semiconductor chip and includes a plurality of second conductive pads provided on its upper surface; and    a plurality of first connecting members for connecting said plurality of first conductive pads to said plurality of second conductive pads,    wherein at least one of said plurality of first connecting members has a resistance value per unit length different from those of the other first connecting members.    
     
     
         5 . The semiconductor device of  claim 4 , wherein at least one of said plurality of first connecting members is made of a material different from those of the other first connecting members.  
     
     
         6 . The semiconductor device of  claim 4 , wherein the number of wires for at least one of said plurality of first connecting members is different from those of the other first connecting members.  
     
     
         7 . A semiconductor device comprising: 
 a first semiconductor chip; and    a second semiconductor chip provided on said first semiconductor chip,    wherein fixing means for disposing said second semiconductor chip is provided on said first semiconductor chip.    
     
     
         8 . The semiconductor device of  claim 7 , wherein said fixing means is a first convex portion with which said second semiconductor chip can engage.  
     
     
         9 . The semiconductor device of  claim 8 , wherein a second convex portion on which said second semiconductor chip can slide is formed at areas on said first semiconductor chip other than the area that said second semiconductor chip is to be disposed.  
     
     
         10 . A semiconductor device comprising: 
 a first semiconductor chip; and    a second semiconductor chip provided on said first semiconductor chip,    wherein said first semiconductor chip has a first engagement portion,    said second semiconductor chip has a second engagement portion, and    said first engagement portion is fitted into said second engagement portion.    
     
     
         11 . The semiconductor device of  claim 10  further comprising a third semiconductor chip provided on said first semiconductor chip, 
 wherein said third semiconductor chip has a third engagement portion,  
 said first semiconductor chip has a fourth engagement portion,  
 said third engagement is fitted into said fourth engagement portion and  
 said first engagement portion has different configuration from said third engagement portion.  
 
     
     
         12 . A semiconductor device comprising: 
 a first semiconductor chip; and    a second semiconductor chip provided on said first semiconductor chip,    wherein a first mark indicating the area said second semiconductor chip is to be disposed is provided on said first semiconductor chip.    
     
     
         13 . The semiconductor device of  claim 12  further comprising a third semiconductor chip provided on said first semiconductor chip, 
 wherein a second mark indicating the area said third semiconductor chip is to be disposed is provided on said first semiconductor chip,  
 said first mark is different from said second mark.  
 
     
     
         14 . A semiconductor device comprising: 
 an internal circuit;    a wire bonding conductive pad connected to said internal circuit; and    a bump connection pad connected to said internal circuit in parallel with said wire bond conductive pad.    
     
     
         15 . The semiconductor device of  claim 14  comprising: 
 a first surface; and  
 a second surface opposing said first surface,  
 wherein said wire bonding conductive pad and said bump connection pad are provided on said first surface.  
 
     
     
         16 . A semiconductor device comprising: 
 a first semiconductor chip that includes a plurality of first conductive pads provided on it upper surface;    a second semiconductor chip provided on said first semiconductor chip that includes a plurality of second conductive pads provided on its upper surface;    a plurality of first connecting members for connecting said plurality of first conductive pads to said plurality of second conductive pads; and    a plurality of second connecting members led from said plurality of second conductive pads, with a ground potential beings supplied thereto.    
     
     
         17 . A method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit, a first conductive pad which is provided on its upper surface and is connected to said first internal circuit and a wire bond island serving as a conductive pad which is provided on its upper surface and is not connected to said first internal circuit; and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to said second internal circuit, wherein said first conductive pad is connected to said second conductive pad, and said first conductive pad is connected to externals, 
 said method comprising the steps of: 
 (a) determining a connection path which can be connected by wire bonding from the connection relationship between said internal circuits and said externals and the positions of said conductive pads; and  
 (b) calculating, with respect to said connection path, the position of said wire bond island provided on said first semiconductor chip.  
   
     
     
         18 . A method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit, at least one first conductive pad which is provided on its upper surface and is connected to said first internal circuit and at least one wire bond island serving as a conductive pad which is provided on its upper surface and is not connected to said first internal circuit; and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to said second internal circuit, wherein said at least one first conductive pad is connected to said second conductive pad, and said at least one first conductive pad is connected to externals, 
 said method comprising the steps of: 
 (a) determining whether or not at least one connection path determined from the connection relationship between said internal circuits and said externals and the positions of said at least one first conductive pad and said second conductive pad can be connected by wire bonding;  
 (b) calculating the position of said at least one wire bond island provided on said first semiconductor chip if it is determined in said step (a) that said at least one connection path can be connected by wire bonding; and  
 (c) if it is determined in said step (a) that said connection path cannot be connected by wire bonding, calculating the position of said at least one wire bond island provided on said first semiconductor chip and then changing the configuration of said at least one wire bond island so that said connection path can be connected by wire bonding.  
   
     
     
         19 . The method for designing semiconductor device of  claim 18 , wherein a plurality of said at least one first conductive pads are provided, 
 said plurality of at least one connection paths are determined in said step (a),    a plurality of the positions of said at least one wire bond islands are obtained in said step (b) or (c),    said method further comprising the step of: 
 (d) with respect to two of said plurality of connection paths, changing the positions of the wire bond islands so that the distances between said first conductive pads and said wire bond islands are equal.  
   
     
     
         20 . A method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a first conductive pad which is provided on its upper surface and is connected to said first internal circuit; and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to said second internal circuit, wherein said first conductive pad is connected to said second conductive pad, and said first conductive pad is connected to externals, 
 said method comprising the steps of: 
 (a) determining a connection path from the connection relationship between the internal circuits and said externals and the positions of the conductive pads;  
 (b) when said connection path is connected by a connecting member, determining whether or not a delay value of said connection path is within a tolerance; and  
 (c) if it is determined in said step (b) that the delay value of said connection path is not within a tolerance, changing the connecting member so that the delay value of said connection path is within a tolerance.  
   
     
     
         21 . The method for designing semiconductor device of  claim 20 , wherein in said step (c), materials for said connecting member are changed so that the delay value of said connection path is within a tolerance.  
     
     
         22 . The method for designing semiconductor device of  claim 20 , wherein in said step (c), the number of wires structuring said connecting member is changed so that the delay value of said connection path is within a tolerance.  
     
     
         23 . A method for designing semiconductor device which comprises a first semiconductor chip and a second semiconductor chip provided on said first semiconductor chip, comprising the steps of: 
 (a) determining the area on said first semiconductor chip that said second semiconductor chip is to be disposed from the arrangement relationship between said first semiconductor chip and said second semiconductor chip and configurations of said first semiconductor chip and second semiconductor chip; and    (b) in order to form a first convex portion with which said second semiconductor chip engages, determining the arrangement of said first convex portion on said first semiconductor chip and the configuration of said first convex portion.    
     
     
         24 . The method for designing semiconductor device of  claim 23  further comprising the step of: 
 (c) in order to form a second convex portion on which said second semiconductor chip can slide, determining the arrangement of said second convex portion on said first semiconductor chip and the configuration of said second convex portion.  
 
     
     
         25 . A method for designing semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on said first semiconductor chip, comprising the steps of: 
 (a) determining the area on said first semiconductor chip that said at least one second semiconductor chip is to be disposed from the arrangement relationship between said first semiconductor chip and said at least one second semiconductor chip and configurations of said first semiconductor chip and said at least one second semiconductor chip;    (b) detecting the number of said at least one second semiconductor chips;    (c) if the number of said at least one second semiconductor chips is 1 in said step (b), determining the positions of a first engagement portion on said first semiconductor chip and a second engagement portion on said second semiconductor chip which is fitted into said first engagement portion and the configurations of said first engagement portion and said second engagement portion; and    (d) if the number of said at least one second semiconductor chips is a plural number in said step (b), determining the positions of said first engagement portions on said first semiconductor chip and said second engagement portions on said second semiconductor chips fitted into said first engagement portions and the configurations of said first engagement portions and said second engagement portions.    
     
     
         26 . A method for designing semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on said first semiconductor chip, comprising the steps of: 
 (a) determining the area on said first semiconductor chip that said at least one second semiconductor chip is to be disposed from the arrangement relationship between said first semiconductor chip and said at least one second semiconductor chip and the configurations of said first semiconductor chip and said at least one second semiconductor chip;    (b) detecting the number of said at least one second semiconductor chips;    (c) if the number of said at least one second semiconductor chips is I in said step (b), determining the configuration of a mark indicating the position on said first semiconductor chip that said second semiconductor chip is to be provided; and    (d) if the number of said at least one second semiconductor chips is a plural number in said step (b), determining the configuration of marks indicating the positions on said first semiconductor chip that said second semiconductor chips are to be provided.    
     
     
         27 . A method for designing semiconductor device which comprises an internal circuit, comprising the step of determining, from a netlist and the configuration of semiconductor chip, the positions of wire bonding pad provided on said semiconductor chip and connected to said internal circuit and bump connection pad connected to said internal circuit in parallel with said wire bonding pad.  
     
     
         28 . A method for designing semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a plurality of first conductive pad provided on its upper surface; and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a plurality of conductive pads provided on it upper surface, 
 wherein said first conductive pads are connected to said second conductive pads, and a ground potential is supplied to at least one of said plurality of first conductive pads,    said method comprising the step of selecting a first conductive pad and a second conductive pad with a ground potential being applied thereto from the connection relationship between the internal circuits and the positions of the conductive pads.    
     
     
         29 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip that includes a first internal circuit, a first conductive pad which is provided on its upper surface and is connected to said first internal circuit and a wire bond island serving as a conductive pad which is provided on its upper surface and is not connected to said first internal circuit and a second semiconductor chip provided on said first semiconductor chip which includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to said second internal circuit, wherein said first conductive pad is connected to said second conductive pad and said first conductive pad is connected to externals, 
 recorded in said recording medium is the program for a computer to perform the steps of: 
 (a) determining a connection path which can be connected by wire bonding from the connection relationship between said internal circuits and said externals and the positions of said conductive pads; and  
 (b) calculating, with respect to said connection path, the position of said wire bond island provided on said first semiconductor chip.  
   
     
     
         30 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip that includes a first internal circuit, at least one first conductive pad which is provided on it upper surface and is connected to said first internal circuit and at least one wire bond island serving as a conductive pad which is provided on its upper surface and is not connected to said first internal circuit and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to said second internal circuit, wherein said at least one first conductive pad is connected to said second conductive pad, and said at least one first conductive pad is connected to externals, 
 recorded in said recording medium is the program for a computer to perform the steps of: 
 (a) determining whether or not at least one connection path determined from the connection relationship between said internal circuits and said externals and the positions of said at least one first conductive pad and said second conductive pad can be connected by wire bonding;  
 (b) if it is determined in said step (a) that said at least one connection path can be connected by wire bonding, calculating the position of said at least one wire bond island provided on said first semiconductor chip; and  
 (c) if it is determined in said step (a) that said connection path cannot be connected by wire bonding, calculating the position of said at least one wire bond island provided on said first semiconductor chip and then changing the configuration of said at least one wire bond island so that said connection path can be connected by wire bonding.  
   
     
     
         31 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a first conductive pad which is provided on it upper surface and is connected to said first internal circuit and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a second conductive pad which is provided on its upper surface and is connected to said second internal circuit, wherein said first conductive pad is connected to said second conductive pad and said first conductive pad is connected to externals, 
 recorded in said recording medium is the program for a computer to perform the steps of: 
 (a) determining a connection path from the connection relationship between said internal circuits and said externals and the positions of said conductive pads;  
 (b) when said connection path is connected by a connecting member, determining whether or not a delay value of said connection path is within a tolerance; and  
 (c) if it is determined in said step (b) that the delay value of said connection path is not within a tolerance, changing the connecting member so that the delay of said connection path is within a tolerance.  
   
     
     
         32 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip and a second semiconductor chip provided on said first semiconductor chip, 
 recorded in said recording medium is the program for a computer to perform the steps of: 
 (a) determining the area on said first semiconductor chip that said second semiconductor chip is to be mounted from the arrangement relationship between said first semiconductor chip and said second semiconductor chip and the configurations of said first semiconductor chip and said second semiconductor chip; and  
 (b) determining the arrangement of a first convex portion on said first semiconductor chip and the configuration of the first convex portion in order to form the first convex portion said second semiconductor chip engages with.  
   
     
     
         33 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on said first semiconductor chip, 
 recorded in said recording medium is the program for a computer to perform the steps of: 
 (a) determining the area on said first semiconductor chip that said at least one second semiconductor chip is to be disposed from the arrangement relationship between said first semiconductor chip and said at least one second semiconductor chip and the configurations of said first semiconductor chip and said at least one second semiconductor chip;  
 (b) detecting the number of said at least one second semiconductor chips;  
 (c) if the number of said at least one second semiconductor chips is 1 in said step (b), determining the positions of a first engagement portion on said first semiconductor chip and a second engagement portion on said second semiconductor chip fitted into said first engagement portion and the configurations of said first engagement portion and said second engagement portion; and  
 (d) if the number of said at least one second semiconductor chips is a plural number in said step (b), determining the positions of said first engagement portions on said first semiconductor chip and said second engagement portions on said second semiconductor chips fitted into said first engagement portions and the configurations of said first engagement portions and said second engagement portions.  
   
     
     
         34 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip and at least one second semiconductor chip provided on said first semiconductor chip, 
 recorded in said recording medium is the program for a computer to perform the steps of: 
 (a) determining the area on said first semiconductor chip that said at least one second semiconductor chip is to be disposed from the arrangement relationship between said first semiconductor chip and said at least one second semiconductor chip and the configurations of said first semiconductor chip and said at least one second semiconductor chip;  
 (b) detecting the number of said at least one second semiconductor chips;  
 (c) if the number of said at least one second semiconductor chips is 1 in said step (b), determining the configuration of a mark indicating the position on said first semiconductor chip that said second semiconductor chip is to be provided; and  
 (d) if the number of said at least one second semiconductor chips is a plural number in said step (b), determining the configuration of marks indicating the positions on said first semiconductor chip that said second semiconductor chips are to be provided.  
   
     
     
         35 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device with an internal circuit, 
 recorded in said recording medium is the program for a computer to perform the step of determining, from a netlist and the configuration of a semiconductor chip, the positions of wire bonding pad provided on said semiconductor chip and connected to said internal circuit and bump connection pad connected to said internal circuit in parallel with said wire bonding pad.    
     
     
         36 . A computer readable recording medium incorporated into a computer used for designing a semiconductor device which comprises a first semiconductor chip that includes a first internal circuit and a plurality of first conductive pads provided on its upper surface and a second semiconductor chip provided on said first semiconductor chip that includes a second internal circuit and a plurality of second conductive pads provided on its upper surface, wherein said first conductive pads are connected to said second conductive pads and a ground potential is supplied to at least one of said plurality of first conductive pads, 
 recorded in said recording medium is the program for a computer to perform the step of selecting a first conductive pad and a second conductive pad with the ground potential being applied thereto from the connection relationship between said internal circuits and the positions of said conductive pads.