Process for fabricating a self-aligned vertical bipolar transistor

Abstract

The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.

What is claimed is:  
     
         1 . A process for fabricating a bipolar transistor comprising the steps of: 
 producing a base region comprising an extrinsic base and an intrinsic base;    producing an emitter region above the intrinsic base comprising an emitter block with a narrower lower part located in an emitter window, the emitter window produced with vertical lateral boundaries; and    implanting dopants in the extrinsic base before the emitter block is formed and after the production of the emitter window, so that dopants are implanted on either side of and at a predetermined distance from the vertical lateral boundaries of the emitter window, so that the extrinsic base is self-aligned with respect to the emitter window.    
     
     
         2 . The process according to  claim 1 , further comprising the process of steps of: 
 forming an insulating layer above the intrinsic base;    etching an orifice in the insulating layer, the orifice etched with dimensions corresponding to dimensions of the emitter window and the orifice etched with vertical lateral edges;    producing an oxide block on the insulating layer formed above the intrinsic base, wherein the oxide block comprises a narrower lower part extending into the orifice etched in the insulating layer, the oxide block comprises a wider upper part resting on the insulating layer, the upper part of the oxide block having vertical lateral walls, so that the vertical lateral edges of the orifice in the insulating layer is self-aligned with the vertical lateral walls of the upper part; and    wherein the step of implanting dopants in of the extrinsic base is carried out on either side of the upper part of the oxide block.    
     
     
         3 . The process according to  claim 2 , wherein the step of producing an oxide block further comprises the sub-steps of: 
 forming a sacrificial layer above the insulating layer;    etching a cavity in the sacrificial layer by photolithography, the cavity whose dimensions correspond to dimensions of the upper part of the oxide block;    forming a set of spacers resting on the insulating layer of the vertical lateral walls, by oxide deposition followed by whole-wafer resinless anisotropic etching, the set of spacers at a separation distance therebetween which defines the dimension of width for the emitter window;    partial etching of the insulating layer between the set of spacers so as to form the orifice;    filling, with oxide, the orifice and a space defined between the set of spacers; and    removing of the sacrificial layer so that the oxide block is left on the insulating layer.    
     
     
         4 . The process according to  claim 3 , wherein the step forming the insulating layer further comprises the sub-steps of: 
 forming a first sub-layer from a first dielectric; and    forming a second sub-layer from a second sub-layer from a second dielectric;    wherein the set of spacers and the oxide block are formed from the first silicon oxide;    wherein the etching of the cavity in the sacrificial layer and the etching of the spacers are carried out so as to stop on the second insulating sub-layer; and    wherein in that the orifice, whose dimensions correspond to those of the emitter window, is etched in the second insulating sub-layer.    
     
     
         5 . The process according to  claim 4 , wherein the step of forming the sacrificial layer includes forming the sacrificial layer from polysilicon.  
     
     
         6 . The process according to  claim 4 , wherein the step of forming the sacrificial layer includes forming the sacrificial layer from silicon-germanium.  
     
     
         7 . The process according to  claim 6 , wherein the step of removing the sacrificial layer comprises removing the sacrificial layer using isotropic plasma etching with a gas mixture consisting of hydrobromic acid and oxygen in a volume ratio of the order of 10, and a pressure greater than 15 mTorr.  
     
     
         8 . The process according to  claim 7 , wherein the step of removing the sacrificial layer comprises removing the sacrificial layer using isotropic plasma etching with a gas mixture consisting of hydrobromic acid and oxygen in a volume ratio of the order of 10, and a pressure greater than 15 mTorr.  
     
     
         9 . The process according to claims  2 , wherein the step of producing an emitter further comprises the sub-steps of: 
 etching of the oxide block and part of the insulating layer which is located in the emitter window;    forming a polysilicon layer on the unetched areas of the insulating layer and on part of the intrinsic base which is located in the emitter window; and    etching of the polysilicon layer so as to form the emitter block.    
     
     
         10 . The process according to  claim 2 , wherein the step of producing the base region includes producing the base region with a SiGe heterojunction and the base region comprises epitaxial growth of a stack of silicon and silicon-germanium layers.  
     
     
         11 . The process according to  claim 11 , wherein the step of producing the emitter region includes producing the emitter region with epitaxial growth, on the emitter window, of the upper surface of the base stack so as to obtain, at least above the said window, an emitter region formed from monocrystalline silicon and directly in contact with the upper layer of the stack.  
     
     
         12 . A bipolar transistor which comprises: 
 a base region comprising an extrinsic base and an intrinsic base;    an emitter region above the intrinsic base comprising an emitter block with a narrower lower part located in an emitter window, the emitter window produced with vertical lateral boundaries; and    dopants implanted in the extrinsic base before the emitter block is formed and after the production of the emitter window, so that dopants are implanted on either side of and at a predetermined distance from the vertical lateral boundaries of the emitter window, so that the extrinsic base is self-aligned with respect to the emitter window.    
     
     
         13 . The bipolar transistor according to  claim 12 , which further comprises: 
 an insulating layer formed above the intrinsic base, wherein an orifice in the insulating layer is etched with dimensions corresponding to dimensions of the emitter window and the orifice etched with vertical lateral edges;    an oxide block produced on the insulating layer formed above the intrinsic base, wherein the oxide block comprises a narrower lower part extending into the orifice etched in the insulating layer, the oxide block comprises a wider upper part resting on the insulating layer, the upper part of the oxide block having vertical lateral walls, so that the vertical lateral edges of the orifice in the insulating layer is self-aligned with the vertical lateral walls of the upper part; and    wherein the dopants implanted in the extrinsic base are implanted on either side of the upper part of the oxide block.    
     
     
         14 . The bipolar transistor according to  claim 13 , in which the oxide block further comprises: 
 a sacrificial layer formed above the insulating layer with a cavity etched in the sacrificial layer by photolithography, the cavity whose dimensions correspond to dimensions of the upper part of the oxide block;    a set of spacers formed resting on the insulating layer of the vertical lateral walls, by oxide deposition followed by whole-wafer resinless anisotropic etching, the set of spacers at a separation distance therebetween which defines the dimension of width for the emitter window;    wherein the orifice is formed by partial etching of the insulating layer between the set of spacers;    oxide filling the orifice and a space defined between the set of spacers; and    means for removing of the sacrificial layer so that the oxide block is left on the insulating layer.