Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus
Abstract
A single gas tight system which performs multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having ( 1 ) a plurality of modules each having a holding fixture, a wafer, a probing device, an electronic circuit board, and a temperature control device, ( 2 ) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, ( 3 ) a handler for moving the wafers and the probing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures and the probing devices. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device. An integrated circuit has a plurality of conductive contact portions that are able to be connected to probe points of the probing device. A temperature control device is used to heat the wafer during an oxide reduction process or during burn-in of the wafer. During the oxide reduction process, hydrogen is introduced into the chamber, and the wafer is heated so that the oxides on the contact pads can combine with hydrogen to form water vapor, thus reducing the thickness of the oxides. The computer analyzes the test and/or burn-in data and provides control signals for repairing or programming the integrated circuits. The computer system also generates a database that contains the performance data of all the integrated circuits on the wafer that are tested and allows for immediate feedback of the quality of the integrated circuits.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A system for processing a plurality of integrated circuits formed on a substrate, each of said integrated circuits having a plurality of conductive contact portions, said system comprising:
a first module having: a probing device having a plurality of probe points for simultaneously contacting substantially all said integrated circuits, said probing device having a support on which said probe points are formed and having circuitry thereon which generate test signals for performing at least one of functional testing, at-speed functional testing and burn-in processing of said integrated circuits; and a fixture which holds said substrate, wherein a maximum travel, in a plane parallel to a principal surface of said substrate, between said fixture and said probing device, is a distance across a limited central portion of said substrate, and said fixture holds said substrate; wherein said first module electrically couples said plurality of probe points of said probing device to said plurality of conductive contact portions of said substrate; and a programmed computer is coupled to said circuitry of said probing device, and utilizes substantially fewer signal lines than a total number of said plurality of probe points of said probing device.
2 . The system of claim 1 , further comprising:
a second module having:
a second probing device having a plurality of probe points for simultaneously contacting substantially all of a plurality of integrated circuits formed on a second substrate, said second probing device having a support having circuitry thereon which generate test signals for performing at least one of functional testing, at-speed functional testing and burn-in processing of said integrated circuits; and
a second fixture which holds said second substrate, wherein a maximum travel, in a plane parallel to a principal surface of said second substrate, between said second fixture and said second probing device, is a distance across a limited central portion of said second substrate, and said second fixture holds said second substrate;
wherein said second module couples said plurality of probe points of said second probing device to said plurality of conductive contact portions of said second substrate; and
said programmed computer is coupled to said circuitry of said second probing device.
3 . The system according to claim 2 , wherein at least one of said first and second modules further comprises a temperature control device which modifies a temperature of at least one of said substrates.
4 . The system according to claim 3 further comprising a gas source coupled to said at least one module.
5 . The system according to claim 2 further comprising a handler to move said substrates.
6 . The system according to claim 6 further comprising:
a chamber enclosing said first and second modules, said handler and said temperature control device, wherein said programmed computer is coupled to said handler, said temperature control device, and said first and second modules.
7 . The system according to claim 2 wherein at least one of said first and second modules further comprises a circuit board coupled to said programmed computer.
8 . The system according to claim 2 further comprising a chamber enclosing said substrates.
9 . The system according to claim 2 wherein at least one of said first and second modules is gas tight.
10 . The system according to claim 2 wherein at least one of said substrates is an entire semiconductor wafer.
11 . The system according to claim 1 wherein said circuitry of said probing device performs functional circuit testing, electrical burn-in, repair, and programming.
12 . The system of claim 1 wherein said circuitry of said probing device performs at least two different functions selected from the group consisting of functional testing, at speed functional testing, burn-in processing, programming, and repair processing.
13 . The system of claim 2 , wherein said circuitry of said probing device performs functional testing and burn-in testing of said integrated circuits.
14 . The system of claim 13 , wherein said probing device is configured to probe an entire semiconductor wafer.
15 . The system of claim 1 wherein said circuitry is configured to test each of said integrated circuits individually.
16 . The system according to claim 15 further comprising:
a gas source coupled to said system said gas source providing a first gas; and
a temperature control device which modifies a temperature of portions of said integrated circuits adjacent said conductive contact portions.
17 . The system according to claim 16 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.
18 . The system according to claim 16 wherein said first module is gas tight.
19 . The system according to claim 15 wherein said circuitry comprises integrated circuitry.
20 . The system according to claim 19 wherein said integrated circuitry comprises active switching circuits.
21 . The system according to claim 15 wherein a number of said plurality of probe points exceeds 10,000.
22 . The system according to claim 15 wherein said probing device further comprises a membrane supporting said plurality of probe points.
23 . The system according to claim 22 wherein said circuitry comprises active switching circuitry.
24 . The system according to claim 22 wherein a number of said plurality of probe points exceeds 10,000.
25 . The system according to claim 22 further comprising:
a gas source for supplying at least a first gas into said system; and
a temperature control device for modifying a temperature in a predetermined area of each of said integrated circuit.
26 . The system according to claim 25 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.
27 . The system according to claim 25 wherein said first module is gas tight.
28 . The system of claim 1 wherein said circuitry is passive only.
29 . The system of claim 1 wherein said circuitry has active switching circuitry.
30 . The system of claim 29 wherein said active switching circuitry causes a given signal line to be coupled to a first of said plurality of probe points at a first time and a second different probe point at a later time.
31 . The system of claim 30 wherein said first and second probe points each correspond to an output pad of one of said integrated circuits.
32 . The system of claim 1 wherein said fixture holds said substrate in a fixed position from a time at which a first of said integrated circuits is processed to a time at which a last of said integrated circuits is processed.
33 . The system of claim 1 wherein said circuitry of said probing device performs both functional testing and burn-in testing of said integrated circuits.
34 . The system according to claim 2 , further comprising a temperature control device which modifies a temperature of one of said substrates, and a gas source.
35 . The system according to claim 34 wherein at least one of said first and second modules further comprises a gas source for supplying at least a non-oxidizing gas.
36 . The system according to claim 34 wherein at least one of said first and second modules further comprises a circuit board coupled to said computer.
37 . The system according to claim 34 wherein at least one of said first and second modules is gas tight.
38 . The system according to claim 1 wherein said computer stores a database of performance data corresponding to each of said integrated circuits.
39 . A system for processing one or more substrates, each of said substrates having a plurality of integrated circuits formed thereon, each of said integrated circuits having a plurality of conductive contact portions, said system comprising:
one or more modules, each of said modules including:
a probing device including a plurality of probe points for simultaneously contacting substantially all said integrated circuits formed on an associated one of said substrates, said probing device having a support having circuitry thereon which generates test signals to perform at least one of functional testing, at-speed functional testing and burn-in testing of said integrated circuits of said associated substrate, wherein said plurality of probe points electrically contact substantially all of said plurality of conductive contact portions of each of said integrated circuits of said associated substrate, and wherein said circuitry is configured to test each of said integrated circuits of said associated substrate individually; and
a fixture which holds said associated substrate, wherein a maximum travel, in a plane parallel to a principal surface of said associated substrate, between said fixture and said probing device, is a distance across a limited central portion of said associated substrate; and
a programmed computer coupled to said circuitry of said probing device of each of said modules, and utilizing substantially fewer signal lines than a total number of said plurality of probe points of said probing device of said modules.
40 . The system according to claim 39 further comprising:
a handler which moves said substrates and moves said probing devices;
wherein each of said modules further includes a circuit board for coupling said programmed computer with said circuitry of said probing device; and
wherein said computer sends signals to and receives signals from said handler, said circuit boards, and said fixtures.
41 . A system for processing a plurality of integrated circuits on a work piece, each of said integrated circuits having a plurality of conductive contact portions, said system comprising:
a probing device including:
a semiconductor substrate,
a plurality of probe points on said semiconductor substrate, each of said probe points being associated with one of said plurality of conductive contact portions, and
a plurality of transistors and interconnects therebetween on said semiconductor substrate, wherein said plurality of transistors and interconnects generates signals for processing at least one of functional testing, at-speed functional testing, and burn-in testing of said plurality of integrated circuits on said work piece substrate; and
a fixture which holds said work piece for coupling said plurality said conductive contact portions to said associated probe points while substantially all of said plurality of integrated circuits are subject to said processing.
42 . A method for processing integrated circuits formed on a substrate, each of said integrated circuits having a plurality of conductive contact portions, said method comprising the acts of:
loading said substrate in a test system and; performing at least three of (a) to (g) while said substrate is in said test system:
(a) reducing an oxide thickness on at least some of said plurality of conductive contact portions;
(b) testing a functionality of at least one of said integrated circuits;
(c) burning-in said substrate;
(d) repairing at least one of said integrated circuits;
(e) programming at least one of said integrated circuits;
(f) marking a symbol on said substrate; and
(g) collecting data corresponding to performance data of at least one of said integrated circuits.
43 . The method of claim 42 wherein the act of testing a functionality comprises the acts of:
transmitting first electrical signals from a computer to a circuit board;
transmitting second electrical signals from said circuit board to processing circuitry of a probing device;
applying third electrical signals from said processing circuitry electronics to said plurality of conductive contact portions of said integrated circuits through a plurality of probe points of said probing device; and
transmitting fourth electrical signals to said computer, said fourth electrical signals produced in response to said third electrical signals.
44 . The method of claim 42 wherein the act of burning in said substrate comprises the act of testing for a predetermined time period over a range of predetermined temperatures and electrical conditions each of said integrated circuits of said first substrate.
45 . The method of claim 42 wherein the act of repairing comprises the acts of:
transmitting electrical signals from a computer to a probing device having a plurality of probe points; and
applying an electrical stimulus via selected ones of said plurality of probe points thereby causing at least one of a fuse circuit device and an anti-fuse circuit device of said substrate to change state.
46 . The method of claim 42 wherein the act of programming comprises the acts of:
transmitting electrical signals from a computer to a probing device having a plurality of probe points; and
applying electrical stimuli via selected ones of said plurality of probe points thereby causing binary values to be stored non-volatilely in said integrated circuits.Join the waitlist — get patent alerts
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