Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

Abstract

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device, comprising the steps of: 
 (a) providing a semiconductor substrate with first conductor patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with grooves formed in self-alignment with said first conductor patterns in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (b) burying a first insulating film in said grooves;    (c) forming a second conductor pattern over said first conductor patterns and said first insulating film;    (d) forming a second insulating film over said second conductor pattern;    (e) forming a conductive film over said second insulating film; and    (f) patterning said conductive film, said second conductor pattern and said first conductor patterns in said peripheral circuit region and in said memory cell forming region,    wherein, in said step (f), the conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell,    wherein, in said step (f), said second conductor pattern and said first conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (f), at least said second conductor pattern and the first conductor pattern of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         2 . A method of manufacturing a semiconductor device according to  claim 1 , further comprising the step of: 
 (g) between said step (d) and said step (e), forming an opening in said second insulating film,    wherein, in said step (e), the conductive film, of said peripheral circuit region, is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         3 . A method of manufacturing a semiconductor device according to  claim 1 , wherein, in said step (b), said first insulating film is comprised of a fluid silicon oxide film containing phosphorus or boron.  
     
     
         4 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) providing a semiconductor substrate with first conductor patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with grooves formed in self-alignment with said first conductor patterns in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (b) burying a first insulating film in said grooves;    (c) forming a second insulating film over said first conductor patterns and said first insulating film;    (d) forming a conductive film over said second insulating film; and    (e) patterning said conductive film and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,    wherein, in said step (e), the conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,    wherein, in said step (e), the first conductor pattern of said memory cell forming region is patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (e), at least the first conductor pattern of said peripheral circuit region is patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         5 . A method of manufacturing a semiconductor device according to  claim 4 , further comprising the step of: 
 (g) between said step (c) and said step (d), forming an opening in said second insulating film,    wherein, in said step (d), the conductive film of said peripheral circuit region is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         6 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) forming first conductor patterns over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;    (b) forming grooves, in self-alignment with said first conductor patterns, in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (c) burying a first insulating film in said grooves;    (d) forming a second conductor pattern over said first conductor patterns and said first insulating film;    (e) forming a second insulating film over said second conductor pattern;    (f) forming a second conductive film over said second insulating film; and    (g) patterning said second conductive film, said second conductor pattern and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,    wherein, in said step (g), said second conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,    wherein, in said step (g), said first conductor patterns and said second conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (g), at least said second conductor pattern and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         7 . A method of manufacturing a semiconductor device according to  claim 6 , wherein in said step (a) each of said first conductor patterns has a third insulating film formed thereover, 
 wherein in said step (b) said grooves are formed in self-alignment with said third insulating film over said first conductor patterns, and    wherein, before said step (c), said third insulating film is removed.    
     
     
         8 . A method of manufacturing a semiconductor device according to  claim 6 , further comprising the step of: 
 (h) between said step (f) and said step (g), forming an opening in said second insulating film,    wherein, in said step (g), the second conductive film, of said peripheral circuit region, is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         9 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) forming first conductor patterns over a memory cell forming region and a peripheral circuit region of a semiconductor substrate;    (b) forming grooves, in self-alignment with said first conductor patterns, in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that said grooves in said peripheral circuit region define an active region of an MISFET in said peripheral circuit region;    (c) burying a first insulating film in said grooves;    (d) forming a second insulating film over said first conductor patterns and said first insulating film;    (e) forming a second conductive film over said second insulating film; and    (f) patterning said second conductive film and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,    wherein, in said step (f), the second conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell,    wherein, in said step (f), said first conductor pattern of said memory cell forming region is patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (f), at least said first conductor pattern of said peripheral circuit region is patterned to form a gate electrode of said MISFET in said peripheral circuit region.    
     
     
         10 . A method of manufacturing a semiconductor device according to  claim 9 , wherein, in said step (a), each of said first conductor patterns includes a third insulating film formed over the first conductor pattern, 
 wherein, in said step (b), said grooves are formed in self-alignment with said third insulating film and said first conductor patterns, and    wherein, before said step (c), said third insulating film is removed.    
     
     
         11 . A method of manufacturing a semiconductor device according to  claim 9 , further comprising the step of: 
 (g) between said step (d) and said step (e), forming an opening in said second insulating film,    wherein, in said step (f), the second conductive film, of said peripheral circuit region, is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.    
     
     
         12 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) forming first conductor patterns over a memory cell forming region of a semiconductor substrate such that said first conductor patterns cover a peripheral circuit region of said semiconductor substrate;    (b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region such that said grooves serve as an element isolation region in said memory cell forming region;    (c) burying a first insulating film in said grooves by polishing an insulating film deposited over said grooves and said peripheral circuit region;    (d) after said step (c), removing said first conductor patterns from said peripheral circuit region;    (e) after said step (d), forming a conductive film over said first conductor patterns and said peripheral circuit region;    (f) patterning said conductive film and said first conductor patterns in said memory cell forming region and patterning said conductive film in said peripheral circuit region; and    (g) forming an element isolation region in said peripheral circuit region such that said step (g) is performed in a different manufacturing step from said steps (b) and (c);    wherein, in said step (f), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell,    wherein, in said step (f), said first conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (f), said conductive film in said peripheral circuit region is patterned to form a gate electrode of a MISFET of said peripheral circuit region.    
     
     
         13 . A method of manufacturing a semiconductor device according to  claim 12 , further comprising the step of: 
 (h) between said steps (a) and (b), forming side wall spacers on side surfaces of said first conductor patterns,    wherein in said step (b) said grooves are formed in self-alignment with said side wall spacers and said first conductive patterns.    
     
     
         14 . A method of manufacturing a semiconductor device according to  claim 12 , wherein in said step (c), said first insulating film is comprised of a fluid silicon oxide film containing phosphorous or boron.  
     
     
         15 . A method of manufacturing a semiconductor device, comprising steps of: 
 (a) forming first conductor patterns over a memory cell forming region of a semiconductor substrate such that said first conductor patterns cover a peripheral circuit region of said semiconductor substrate;    (b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region such that said grooves serve as an element isolation region in said memory cell forming region;    (c) burying a first insulating film in said grooves by polishing an insulating film deposited over said grooves and said peripheral circuit region;    (d) after said step (c), forming a conductive film over said first conductor patterns and said peripheral circuit region; and    (e) patterning said conductive film and said first conductor patterns in said memory cell forming region and patterning said conductive film in said peripheral circuit region;    wherein, in said step (e), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell,    wherein, in said step (e), said first conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and    wherein, in said step (e), said conductive film in said peripheral circuit region is patterned to form a gate electrode of a MISFET of said peripheral circuit region.    
     
     
         16 . A method of manufacturing a semiconductor device according to  claim 15 , wherein in said step (c), said first insulating film is comprised of a fluid silicon oxide film containing phosphorous or boron.  
     
     
         17 . A semiconductor device having first MISFETs constituting memory cells, said first MISFETs including a first floating gate electrode formed on a main surface of a semiconductor substrate through a gate insulating film, a control gate electrode formed overlying an upper portion of said first floating gate electrode through an interlayer insulating film, and a pair of semiconductor regions formed in said semiconductor substrate and serving as source/drain regions, 
 wherein said first MISFETs adjoining in a first direction are isolated by means of a first isolation region having a structure formed by burying a groove of said semiconductor substrate with a first insulating film, said first insulating film having an upper surface higher than said main surface of said semiconductor substrate,    wherein a second floating gate electrode is formed on said upper portion of said first floating gate electrode and is electrically connected with said first floating gate electrode, said interlayer insulating film being formed on said second floating gate electrode, said second floating gate electrode being arranged to extend on said upper surface of said first insulating film, and said upper surface of said first insulating film being higher than said upper portion of said first floating gate electrode,    wherein a first voltage is applied to said control gate electrode during a write operation, and    wherein said first voltage applied to said control gate electrode during the write operation has three or more voltage levels, and changes in threshold level of said first MISFETs logically correspond to said voltage levels on the basis of a difference in amount of charges injected into said first floating gate electrode, whereby information of two bits or more is memorized in one memory cell.    
     
     
         18 . A semiconductor device according to  claim 17 , wherein the first voltage is of a polarity different from a second voltage applied to said control gate electrode during an erase operation; and, for the write operation, where electrons are transferred from said semiconductor substrate to said first floating gate electrode by tunneling through said gate insulating film, the semiconductor regions of selected first MISFETs are set at a same potential as the semiconductor substrate portion below said first floating gate electrode so that the channel region is inverted, and a third voltage of a same polarity as said first voltage is applied to the semiconductor regions of non-selected first MISFETs so that a voltage between the channel region and the control gate electrode thereof is made lower than a potential between the channel region and the control gate electrode of the selected first MISFETs.  
     
     
         19 . A semiconductor device according to  claim 17 , wherein for the writing of information in said one memory cell, the writing is performed to shift from a write operation at a highest first voltage to a write operation at a lower first voltage.  
     
     
         20 . A semiconductor device according to  claim 17 , wherein, for reading of information from said one memory cell, the reading is performed to shift from detection of a threshold level corresponding to an amount of charges injected at the lowest first voltage to detection of a threshold level corresponding to an amount of charges injected at a high first voltage.  
     
     
         21 . A method of manufacturing a semiconductor device, comprising steps of: 
 providing a substrate having conductive patterns formed over a main surface of said substrate and having grooves formed in said substrate such that said grooves are formed in self-alignment with said conductive patterns;    forming an insulating film over a surface of said grooves and said conductive patterns;    forming a fluid silicon oxide film containing phosphorus or boron to cover said grooves, said insulating film and said conductive patterns;    removing said fluid silicon oxide film to fill said fluid silicon oxide film in said grooves; and    thermally treating a surface of said fluid silicon oxide film in an atmosphere of ammonia.    
     
     
         22 . A method of manufacturing a semiconductor device according to  claim 21 , wherein said insulating film is formed to cover said electrodes in said insulating film forming step.  
     
     
         23 . A method of manufacturing a semiconductor device according to  claim 22 , wherein said electrodes are used as floating gate electrodes of a semiconductor non-volatile memory element.  
     
     
         24 . A method of manufacturing a semiconductor device according to  claim 21 , wherein said insulating film is a silicon oxide film.  
     
     
         25 . A method of manufacturing a semiconductor device, comprising steps of: 
 providing a substrate having conductive patterns formed over a main surface of said substrate;    forming an insulating film to cover said conductive patterns;    forming a fluid silicon oxide film containing phosphorus or boron over said main surface, said insulating film and said conductive patterns;    removing said fluid silicon oxide film to fill said fluid silicon oxide film between said conductive patterns; and    thermally treating a surface of said fluid silicon oxide film in an atmosphere of ammonia.    
     
     
         26 . A method of manufacturing a semiconductor device according to  claim 25 , wherein said electrodes are used as floating gate electrodes of a semiconductor non-volatile memory element.  
     
     
         27 . A method of manufacturing a semiconductor device according to  claim 25 , wherein said insulating film is a silicon oxide film.  
     
     
         28 . A method of manufacturing a semiconductor device comprising steps of: 
 providing a substrate having grooves formed in a substrate;    depositing a first insulating film within said grooves and over a main surface of said substrate;    forming a second insulating film to cover said grooves, said first insulating film and said main surface of said substrate;    removing said second insulating film to fill said film in said grooves; and    introducing nitrogen in said second insulating film.    
     
     
         29 . A semiconductor device according to  claim 28 , wherein said nitrogen introducing step is performed by thermally treating a surface of said second insulating film in an atmosphere of ammonia to reduce etching rate of said insulating film.  
     
     
         30 . A semiconductor device according to  claim 29 , wherein said second insulating film includes a fluid silicon oxide film containing phosphorus or boron.  
     
     
         31 . A semiconductor device according to  claim 28 , wherein said substrate further includes conductive patterns formed over said main surface of said substrate, wherein said first insulating film is formed to cover said conductive patterns.  
     
     
         32 . A semiconductor device according to  claim 31 , wherein said second insulating film includes a fluid silicon oxide film containing phosphorus or boron.  
     
     
         33 . A semiconductor device according to  claim 32 , wherein said nitrogen introducing step is performed by thermally treating a surface of said second insulating film in an atmosphere of ammonia to reduce etching rate of said insulating film.