FeRAM capacitor stack etch

Abstract

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl 3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF 3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

What is claimed is:  
     
         1 . A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising: 
 forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;    patterning the hard mask layer;    patterning the top electrode layer in accordance with the patterned hard mask;    patterning the PZT ferroelectric layer using a BCl 3  etch at a substantially high temperature in accordance with the patterned hard mask; and    patterning the bottom electrode layer in accordance with the patterned hard mask.    
     
     
         2 . The method of  claim 1 , wherein patterning the PZT ferroelectric layer comprises using a BCl 3  etch at a temperature of at least 150° C.  
     
     
         3 . The method of  claim 2 , wherein patterning the PZT ferroelectric layer comprises using a BCl 3  etch at a temperature of about 350° C., wherein the patterning of the PZT layer is substantially selective with respect to the patterned hard mask.  
     
     
         4 . The method of  claim 3 , further comprising adding Ar to the BCl 3  etch of the PZT ferroelectric layer, wherein a ratio of BCl 3  to Ar comprises about 1:1.  
     
     
         5 . The method of  claim 2 , further comprising adding Ar to the BCl 3  etch of the PZT ferroelectric layer, wherein a ratio of BCl 3  to Ar comprises about 20% Ar or more and about 30% Ar or less.  
     
     
         6 . A method of forming a capacitor stack in a ferroelectric memory cell, comprising: 
 forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;    patterning the hard mask layer;    patterning the top electrode layer using a Cl 2 +O 2  or a Cl 2 +CO etch in accordance with the patterned hard mask;    patterning the PZT ferroelectric layer using a BCl 3 +Ar etch at a temperature of about 150° C. or more in accordance with the patterned hard mask; and    patterning the bottom electrode layer using a Cl 2 +O 2  or a Cl 2 +CO etch in accordance with the patterned hard mask.    
     
     
         7 . The method of  claim 6 , wherein patterning the top electrode layer, the PZT ferroelectric layer and the bottom electrode layer is performed at a temperature of about 350° C. or more.  
     
     
         8 . The method of  claim 6 , wherein the hard mask layer comprises TiAlN, and wherein an oxygen content in the Cl 2 +O 2  or the Cl 2 +CO etch of the top and bottom electrode layers is at least about 5%, thereby providing a substantial etch selectivity of the capacitor stack with respect to the patterned TiAlN hard mask.  
     
     
         9 . The method of  claim 8 , wherein the temperature of the BCl 3 +Ar PZT ferroelectric layer etch is about 350° C., thereby providing a substantial etch selectivity of the PZT ferroelectric layer with respect to the patterned TiAlN hard mask.  
     
     
         10 . The method of  claim 9 , wherein a ratio of BCl 3  to Ar in the PZT ferroelectric layer etch comprises about 1:1.  
     
     
         11 . The method of  claim 6 , wherein a ratio of BCl 3  to Ar in the PZT ferroelectric layer etch comprises about 20% Ar or more and about 30% Ar or less.  
     
     
         12 . A method of forming a capacitor stack in a ferroelectric memory cell, comprising: 
 forming an iridium bottom electrode layer, a PZT ferroelectric layer, an iridium top electrode layer, and a TiAlN hard mask layer over a substrate;    patterning the TiAlN hard mask layer using a BCl 3  etch;    patterning the iridium top electrode layer using a Cl 2 +O 2  or a Cl 2 +CO etch in accordance with the patterned hard mask, wherein an oxygen content in the iridium top electrode layer etch is at least about 5%, thereby providing a substantial etch selectivity with respect to the TiAlN hard mask;    patterning the PZT ferroelectric layer using a BCl 3 +Ar etch at a temperature of about 150° C. or more in accordance with the patterned hard mask, wherein the temperature of about 150° C. or more provides for an etch of the PZT ferroelectric dielectric layer that is substantially selective with respect to the TiAlN hard mask; and    patterning the bottom electrode layer using a Cl 2 +O 2  or a Cl 2 +CO etch in accordance with the patterned hard mask, wherein an oxygen content in the iridium bottom electrode layer etch is at least about 5%, thereby providing a substantial etch selectivity with respect to the TiAlN hard mask.    
     
     
         13 . The method of  claim 12 , wherein patterning the PZT ferroelectric layer comprises using the BCl 3 +Ar etch at a temperature of at about 350° C.  
     
     
         14 . The method of  claim 13 , wherein a ratio of BCl 3  to Ar comprises about 1:1.  
     
     
         15 . The method of  claim 12 , wherein the temperature of the PZT ferroelectric layer etch is about 150° C., and wherein a ratio of BCl 3  to Ar comprises about 20% Ar or more and about 30% Ar or less.  
     
     
         16 . A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising: 
 forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;    patterning the hard mask layer;    patterning the top electrode layer in accordance with the patterned hard mask;    patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees; and    patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 degrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch.    
     
     
         17 . The method of  claim 16 , wherein patterning the PZT ferroelectric layer comprises etching using a fluorine gas+Cl 2 +an oxidizer at a relatively low temperature.  
     
     
         18 . The method of  claim 17 , wherein the temperature of the PZT ferroelectric layer etch is about 60° C.  
     
     
         19 . The method of  claim 17 , wherein etching the PZT ferroelectric layer comprises using a CHF 3 +Cl 2 +O 2 +N 2  at a temperature of about 60° C.  
     
     
         20 . The method of  claim 16 , wherein patterning the top and bottom electrode layers comprise etching with a Cl 2 +O 2  or a Cl 2 +CO at substantially high temperature, and wherein patterning the PZT ferroelectric layer comprises etching using a fluorine gas+Cl 2 +an oxidizer at a relatively low temperature.  
     
     
         21 . The method of  claim 20 , wherein the substantially high temperature comprises about 350° C., and the relatively low temperature comprises about 60° C.  
     
     
         22 . The method of  claim 16 , wherein the sidewall edge profile angle of the PZT ferroelectric layer is about 80 degrees or more.