Novel method of fabricating metallic local interconnections that also improves transistor performance

Abstract

A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si 3 N 4 ) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO 2 ) insulating layer is deposited and polished back to the Si 3 N 4 cap. The Si 3 N 4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO 2 layer. After etching contact openings in the SiO 2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections. Portions of the metal are retained in the recesses over the pattered polysilicon layer to improve transistor performance, while portions of the metal in the contact openings provide low-contact resistance to the substrate.

What is claimed is:  
     
         1 . A method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity comprising the steps of: 
 providing a semiconductor substrate;    forming field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;    forming a gate oxide on said device areas;    depositing a conductively doped polysilicon layer on said substrate;    depositing a first insulating layer on said polysilicon layer;    patterning said first insulating layer and said polysilicon layer using a photoresist mask and anisotropic plasma etching leaving portions over said device areas to form said gate electrodes and portions of said patterned polysilicon over said field oxide isolation regions for local interconnections;    forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;    depositing a conformal second insulating layer over said gate electrodes and elsewhere on said substrate;    anisotropically etching back said second insulating layer thereby forming sidewall spacers on sidewalls of said gate electrodes;    forming source/drain contact areas by ion implantation;    depositing a third insulating layer on said substrate;    polishing back said third insulating layer to said first insulating layer to form a planar surface;    selectively removing portions of said first insulating layer over said patterned polysilicon layer while leaving essentially unetched said second and said third insulating layers and forming recesses in said third insulating layer over said patterned polysilicon layer;    using a photoresist mask and anisotropic etching to etch contact openings in said third insulating layer to said substrate;    depositing a blanket metal layer and filling said contact openings and said recesses in said third insulating layer over said patterned polysilicon layer;    patterning said metal layer leaving portions over said contact openings and over and contacting portions of said patterned polysilicon layer to complete said local metal interconnections while leaving said metal in said recesses to improve the electrical conductivity of said patterned polysilicon layer.    
     
     
         2 . The method of  claim 1 , wherein said conductively doped polysilicon layer is doped with arsenic to a dopant concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .  
     
     
         3 . The method of  claim 1 , wherein said conductively doped polysilicon layer is deposited to a thickness of between about 150 and 4000 Angstroms.  
     
     
         4 . The method of  claim 1 , wherein said first insulating layer is silicon nitride and is deposited to a thickness of between about 1000 and 3500 Angstroms.  
     
     
         5 . The method of  claim 1 , wherein said second insulating layer and said third insulating layer are silicon oxide.  
     
     
         6 . The method of  claim 4 , wherein said silicon nitride first insulating layer is selectively removed using a hot phosphoric acid etch.  
     
     
         7 . The method of  claim 1 , wherein said contact openings are selectively etched to said substrate using anisotropic plasma etching and an etchant gas mixture composed of trifluoromethane, carbon monoxide, and oxygen.  
     
     
         8 . The method of  claim 1 , wherein said metal layer is a multilayer composed of a titanium/titanium nitride barrier layer and an upper layer of aluminum-copper alloy.  
     
     
         9 . The method of  claim 1 , wherein said metal layer is a multilayer composed of a titanium/titanium nitride barrier layer and an upper layer of copper.  
     
     
         10 . The method of  claim 8 , wherein said barrier layer is deposited to a thickness of between about 50 and 1000 Angstroms, and said aluminum-copper is deposited to a thickness of between about 1500 and 8000 Angstroms.  
     
     
         11 . A method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity comprising the steps of: 
 providing a semiconductor substrate;    forming field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;    forming a gate oxide on said device areas;    depositing a conductively doped polysilicon layer on said substrate;    depositing a silicon nitride first insulating layer on said polysilicon layer;    patterning said first insulating layer and said polysilicon layer using a photoresist mask and anisotropic plasma etching leaving portions over said device areas to form said gate electrodes and portions of said patterned polysilicon over said field oxide isolation regions for local interconnections;    forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;    depositing a conformal silicon oxide second insulating layer over said gate electrodes and elsewhere on said substrate;    anisotropically etching back said second insulating layer thereby forming sidewall spacers on sidewalls of said gate electrodes;    forming source/drain contact areas by ion implantation;    depositing a silicon oxide third insulating layer on said substrate;    polishing back said third insulating layer to said first insulating layer to form a planar surface;    selectively removing portions of said silicon nitride first insulating layer over said patterned polysilicon layer while leaving essentially unetched said second and said third insulating layers and forming recesses in said third insulating layer over said patterned polysilicon layer;    using a photoresist mask and anisotropic etching to etch contact openings in said third insulating layer to said substrate;    depositing a blanket metal layer and filling said contact openings and said recesses in said third insulating layer over said patterned polysilicon layer;    patterning said metal layer leaving portions over said contact openings and over and contacting portions of said patterned polysilicon layer to complete said local metal interconnections while leaving said metal in said recesses to improve the electrical conductivity of said patterned polysilicon layer.    
     
     
         12 . The method of  claim 11 , wherein said conductively doped polysilicon layer is doped with arsenic to a dopant concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .  
     
     
         13 . The method of  claim 11 , wherein said conductively doped polysilicon layer is deposited to a thickness of between about 150 and 4000 Angstroms.  
     
     
         14 . The method of  claim 11 , wherein said silicon nitride first insulating layer is deposited to a thickness of between about 1000 and 3500 Angstroms.  
     
     
         15 . The method of  claim 11 , wherein said second insulating and said third insulating layers composed of silicon oxide are deposited by low-pressure chemical vapor deposition.  
     
     
         16 . The method of  claim 11 , wherein said silicon nitride first insulating layer is selectively removed using a hot phosphoric acid etch.  
     
     
         17 . The method of  claim 11 , wherein said contact openings are selectively etched to said substrate using anisotropic plasma etching and an etchant gas mixture composed of trifluoromethane, carbon monoxide, and oxygen.  
     
     
         18 . The method of  claim 11 , wherein said metal layer is a multilayer composed of a titanium/titanium nitride barrier layer and an upper layer of aluminum-copper alloy.  
     
     
         19 . The method of  claim 11 , wherein said metal layer is a multilayer composed of a titanium/titanium nitride barrier layer and an upper layer of copper.  
     
     
         20 . The method of  claim 18 , wherein said barrier layer is deposited to a thickness of between about 50 and 1000 Angstroms, and said aluminum-copper is deposited to a thickness of between about 1500 and 8000 Angstroms.  
     
     
         21 . A method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity comprising the steps of: 
 providing a semiconductor substrate;    forming field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;    forming a gate oxide on said device areas;    depositing a conductively doped polysilicon layer on said substrate;    depositing a first insulating layer on said polysilicon layer;    patterning said first insulating layer and said polysilicon layer using a-photoresist mask and anisotropic plasma etching leaving portions over said device areas to form said gate electrodes and portions of said patterned polysilicon over said field oxide isolation regions for local interconnections;    forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;    depositing a conformal second insulating layer over said gate electrodes and elsewhere on said substrate;    anisotropically etching back said second insulating layer thereby forming sidewall spacers on sidewalls of said gate electrodes;    forming source/drain contact areas by ion implantation;    depositing a third insulating layer on said substrate;    polishing back said third insulating layer to said first insulating layer to form a planar surface;    using a photoresist mask to selectively remove portions of said first insulating layer over said patterned polysilicon layer while leaving essentially unetched said second and said third insulating layers and forming recesses in said third insulating layer over said patterned polysilicon layer;    using a photoresist mask and anisotropic etching to etch contact openings in said third insulating layer to said substrate;    depositing a blanket metal layer and filling said contact openings and said recesses in said third insulating layer over said patterned polysilicon layer;    patterning said metal layer leaving portions over said contact openings and over and contacting portions of said patterned polysilicon layer to complete said local metal interconnections while leaving said metal in said recesses to improve the electrical conductivity of said patterned polysilicon layer, and further portions of said patterned metal layer extending over remaining said silicon nitride layer to form crossovers for said local interconnections.    
     
     
         22 . The method of  claim 21 , wherein said conductively doped polysilicon layer is doped with arsenic to a dopant concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .  
     
     
         23 . The method of  claim 21 , wherein said conductively doped polysilicon layer is deposited to a thickness of between about 150 and 4000 Angstroms.  
     
     
         24 . The method of  claim 21 , wherein said first insulating layer is silicon nitride and is deposited to a thickness of between about 1000 and 3500 Angstroms.  
     
     
         25 . The method of  claim 21 , wherein said second insulating layer and said third insulating layer are silicon oxide.  
     
     
         26 . The method of  claim 24 , wherein said silicon nitride first insulating layer is selectively removed using a hot phosphoric acid etch.  
     
     
         27 . The method of  claim 21 , wherein said contact openings are selectively etched to said substrate using anisotropic plasma etching and an etchant gas mixture composed of trifluoromethane, carbon monoxide, and oxygen.  
     
     
         28 . The method of  claim 21 , wherein said metal layer is a multilayer composed of a titanium/titanium nitride barrier layer and an upper layer of aluminum-copper alloy.  
     
     
         29 . The method of  claim 21 , wherein said metal layer is a multilayer composed of a titanium/titanium nitride barrier layer and an upper layer of copper.  
     
     
         30 . The method of  claim 28 , wherein said barrier layer is deposited to a thickness of between about 50 and 1000 Angstroms, and said aluminum-copper is deposited to a thickness of between about 1500 and 8000 Angstroms.  
     
     
         31 . A local metal interconnect structure with low contact resistance and FET gate electrodes with improved electrical conductivity comprised of: 
 a semiconductor substrate;    field oxide isolation regions surrounding and electrically isolating device areas and coplanar with surface of said substrate;    a gate oxide on said device areas;    a patterned conductively doped polysilicon layer on said substrate for said FET gate electrodes and portions of said local interconnections, wherein said FET gate electrodes have lightly doped source/drain areas adjacent to said gate electrodes and source/drain contact areas;    an insulating layer having a planar surface on said patterned polysilicon layer and said insulating layer having self-aligned recesses over said patterned polysilicon layer, and said insulating layer having contact openings to said substrate;    a patterned metal layer having portions over and in said contact openings and over and in said recesses to improve the electrical conductivity of said patterned polysilicon layer, and said patterned metal layer also extending over said insulating layer to complete said local metal interconnections.    
     
     
         32 . The structure of  claim 31 , wherein said recesses have portions of silicon nitride over said patterned polysilicon layer for providing electrical crossovers for said patterned metal layer.  
     
     
         33 . The structure of  claim 31 , wherein said conductively doped polysilicon layer is doped with arsenic to a dopant concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 , and has a thickness of between about 150 and 4000 Angstroms.  
     
     
         34 . The structure of  claim 31 , wherein said insulating layer is silicon oxide deposited by low-pressure chemical vapor deposition.  
     
     
         35 . The structure of  claim 31 , wherein said patterned metal layer is composed of a multilayer of a titanium/titanium nitride barrier layer and an upper layer of aluminum-copper alloy.