Semiconductor integrated circuit and a burn-in method thereof

Abstract

The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other. The second circuit has a plurality of level shift circuits capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit, a plurality of external output buffers receiving outputs of the level shift circuits, bypasses for bypassing an input of a predetermined level shift circuit to an input of a predetermined external output buffer, and a selecting circuit for selecting connection of either the predetermined level shift circuit or a bypass to an input of the predetermined external output buffer. In a use form in which the first and second circuits operate with a low voltage, the bypass is selected. In high-voltage operation and burn-in, the level shift circuits are selected.

What is claimed is:  
     
         1 . A semiconductor integrated circuit comprising: 
 a first circuit; and    a second circuit having a breakdown voltage higher than a breakdown voltage of said first circuit, in which operation voltages of said first and second circuits can be made equal to each other or different from each other,    wherein said second circuit comprises: 
 a plurality of level shift circuits capable of shifting the level of an output of said first circuit in accordance with an operation voltage of said second circuit;  
 a plurality of external output buffers receiving outputs of said level shift circuits;  
 a bypass circuit bypassing an input of a predetermined level shift circuit to an input of a predetermined external output buffer; and  
 a selecting circuit selecting connection of either said predetermined level shift circuit or a bypass to an input of said predetermined external output buffer.  
   
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , wherein said level shift circuit is constructed by a plurality of level shift circuits having level shifting ranges which are different from each other.  
     
     
         3 . The semiconductor integrated circuit according to  claim 1 , further comprising: 
 an internal power step-down circuit stepping down an input voltage from a first external terminal,    wherein said second circuit uses an input voltage supplied to the first external terminal as an operation voltage, and    wherein said first circuit uses, as an operation power, a stepped-down output voltage of said internal power step-down circuit or an input voltage from a second external terminal.    
     
     
         4 . The semiconductor integrated circuit according to  claim 3 , 
 wherein when the operation voltage of the first circuit and that of the second circuit are made different from each other, an external power supply voltage is connected to a first terminal and a stabilized capacitative element is coupled to a second terminal, and    wherein when the operation voltage of the first circuit and that of the second circuit are made equal to each other, the same external power supply voltage is coupled to the first and second terminals.    
     
     
         5 . The semiconductor integrated circuit according to  claim 1 , wherein said first circuit has a register holding selection control information of said selecting circuit.  
     
     
         6 . The semiconductor integrated circuit according to  claim 1 , wherein said first circuit has an output latch circuit latching output data of said predetermined external output buffer synchronously with a clock signal and a data processing circuit for processing data to be latched by said output latch circuit.  
     
     
         7 . The semiconductor integrated circuit according to  claim 6 , wherein said output latch circuit is included in a predetermined  10  port.  
     
     
         8 . The semiconductor integrated circuit according to  claim 6 , wherein said output latch circuit is neighboring to said predetermined external output buffer.  
     
     
         9 . The semiconductor integrated circuit according to  claim 6 , wherein said clock signals are supplied from the outside in parallel to said output latch circuit and said data processing circuit.  
     
     
         10 . The semiconductor integrated circuit according to  claim 6 , wherein said data processing circuit is a host interface control circuit.  
     
     
         11 . The semiconductor integrated circuit according to  claim 10 , wherein said host interface control circuit and said output latch circuit operate synchronously with said external clock signal of 33 MHz.  
     
     
         12 . A burn-in method of performing burn-in in a semiconductor integrated circuit comprising a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of said first circuit, in which operation voltages of said first and second circuits can be made equal to each other or different from each other, and said second circuit comprises a level shift circuit capable of shifting the level of an output of said first circuit in accordance with an operation voltage of said second circuit, an external output buffer receiving an output of said level shift circuit, and a bypass for selectively bypassing an input of a predetermined level shift circuit to an input of the external output buffer, 
 wherein operation voltages of the first and second circuits are made different from each other and no bypass selection is set in said bypass.    
     
     
         13 . A semiconductor integrated circuit comprising: 
 an external output buffer;    a latch circuit latching data to be output from said external output buffer synchronously with an external clock signal; and    a circuit processing data to be latched by said latch circuit,    wherein said latch circuit and said processing circuit commonly receive an output of a clock buffer receiving said external clock signal.    
     
     
         14 . The semiconductor integrated circuit according to  claim 13 , wherein said latch circuit is disposed close to said external output buffer.  
     
     
         15 . The semiconductor integrated circuit according to  claim 13 , further comprising: 
 an IO port capable of latching data to be output from said external output buffer synchronously with an internal clock signal,    wherein operation of said IO port and operation of said latch circuit can be selectively switched.    
     
     
         16 . A semiconductor integrated circuit comprising: 
 a central processing unit;    a clock generating circuit receiving a reference clock and generating an operation clock to be supplied to said central processing unit;    an internal bus coupled to said central processing unit;    a host interface module coupled to said internal bus and including: 
 a plurality of output buffers,  
 a plurality of latch circuits latching data to be output from said plurality of output buffers synchronously with an external clock signal, and  
 a processing circuit processing data to be latched by said plurality of latch circuits; and  
   an external terminal to which said external clock signal is supplied from the outside,    wherein said plurality of latch circuits are disposed near said plurality of output buffers, and    wherein said external clock signal supplied to said external terminal is commonly input to said plurality of latch circuits.    
     
     
         17 . The semiconductor integrated circuit according to  claim 16 , wherein said host interface module is a host interface module for an LPC (Low Pin Count) bus interface.  
     
     
         18 . The semiconductor integrated circuit according to  claim 17 , further comprising: 
 an IO port capable of latching data to be output from said plurality of output buffers synchronously with an internal clock signal which is output from said clock generating circuit,    wherein operation of said IO port and operation of said latch circuit can be selectively switched.    
     
     
         19 . The semiconductor integrated circuit according to  claim 17 , further comprising: 
 an AD converter coupled to said internal bus and converting an analog signal supplied from the outside to a digital signal,    wherein said host interface module supplies said digital signal converted by said A/D converter to a host processor to be coupled to said semiconductor integrated circuit.