Field effect transistor structure with partially isolated source/drain junctions and methods of making same

Abstract

A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.

What is claimed is:  
     
         1 . A method of forming a source/drain terminal, comprising: 
 masking a portion of a semiconductor surface;    forming a recess in the semiconductor surface, adjacent to the masked portion, the recess having a bottom portion and a side portion;    implanting ions into the bottom portion; and    selectively forming an undoped silicon layer disposed at least partially within the recess.    
     
     
         2 . The method of  claim 1 , wherein masking a portion of the semiconductor surface comprises forming a gate electrode having multi-layer sidewall spacers and a barrier layer superjacent the gate electrode, wherein the barrier layer comprises silicon oxynitride.  
     
     
         3 . The method of  claim 2 , wherein the gate electrode comprises polysilicon and the barrier layer further comprises silicon dioxide.  
     
     
         4 . The method of  claim 1 , wherein forming a recess comprises plasma etching for approximately 15 seconds, in a parallel plate plasma reactor having a plate spacing of approximately 0.8 cm, a pressure of approximately 475 mT, an RF power of approximately 300 W, a Cl flow rate of 150 sccm, and a He flow rate of approximately 100 sccm.  
     
     
         5 . The method of  claim 4 , wherein implanting ions comprises implanting nitrogen.  
     
     
         6 . The method of  claim 1 , wherein implanting ions comprises implanting carbon.  
     
     
         7 . A method of forming a source/drain terminal, comprising: 
 masking a portion of the semiconductor surface;    forming a recess in the semiconductor surface adjacent to the masked portion, the recess having a bottom portion and a side portion;    forming a dielectric material over the bottom portion of the recess such that the side portion of the recess is substantially exposed; and    selectively forming a layer comprising silicon, beginning at the side portion of the recess and extending laterally away from the side portion.    
     
     
         8 . The method of  claim 7 , wherein masking a portion of the semiconductor surface comprises forming a gate electrode having sidewall spacers and a barrier layer superjacent the gate electrode.  
     
     
         9 . The method of  claim 8 , wherein the gate electrode comprises polysilicon; the sidewall spacers comprise an oxide layer and a nitride layer; and the barrier layer comprises silicon oxynitride.  
     
     
         10 . The method of  claim 7 , wherein forming a recess comprises plasma etching for approximately 15 seconds, in a parallel plate plasma reactor having a plate spacing of approximately 0.8 cm, a pressure of approximately 475 mT, an RF power of approximately 300 W, a Cl flow rate of 150 sccm, and a He flow rate of approximately 100 sccm.  
     
     
         11 . The method of  claim 7 , wherein the dielectric material comprises silicon nitride.  
     
     
         12 . The method of  claim 7 , wherein the dielectric material comprises silicon carbide.  
     
     
         13 . The method of  claim 10 , wherein forming a dielectric material over the bottom portion of the recess comprises forming a morphologically nonconformal silicon nitride layer, the layer covering the bottom portion of the recess and the side portion of the recess, and wherein a portion of the layer covering the bottom portion of the recess is thicker and denser than a portion of the layer covering the side portion of the recess.  
     
     
         14 . The method of  claim 13 , further comprising removing the portion of the layer covering the side portion of the recess.  
     
     
         15 . The method of  claim 14 , wherein removing comprises etching in trimix.  
     
     
         16 . The method of  claim 7 , further comprising, prior to selectively forming a layer comprising silicon, cleaning the recess in an SF 6  plasma.  
     
     
         17 . A microelectronic structure, comprising: 
 a substrate comprising a first crystalline material of a first conductivity type the substrate having at least one recessed portion, the at least one recessed portion having a bottom surface and a side surface;    an insulating layer disposed on the bottom portion surface; and    a second, substantially crystalline, material having a second conductivity type disposed superjacent the insulating material and adjacent a second portion of the substrate wherein the second material substantially fills the at least one recess.    
     
     
         18 . The structure of  claim 17 , wherein the first crystalline material is silicon, and the insulating layer comprises a material selected from the group consisting of silicon nitride and silicon carbide.  
     
     
         19 . The structure of  claim 18 , wherein the second material comprises a material selected from the group consisting of silicon and silicon germanium.