Method for creating a design verification test bench

Abstract

A method for creating test benches for digital circuit design verification (1) partitions a design for purposes of test bench creation according to circuit type, (2) identifies circuit types and creates packaged testing strategies, (3) uses ATPG techniques to create comprehensive test sequences based on the circuit type classifications, and (4) incorporates the ATPG-produced test stimuli and expected responses into the test bench templates.

What is claimed is:  
     
         1 . A method for creating a test bench, comprising the steps of: 
 providing a circuit design expressed in an HDL;    classifying the various parts of the HDL circuit design according to predetermined circuit-types;    providing a test bench HDL design template library in which each template corresponds to a predetermined circuit-type;    selecting library templates that correspond to classified parts of the HDL circuit design;    merging the selected templates into a master template to form a functional verification test bench for the HDL circuit design; and    returning the functional verification test bench.    
     
     
         2 . The method as set forth in  claim 1 , including the additional steps of: 
 providing a plurality of ATPG tools;    providing a virtual circuit netlist corresponding to the HDL circuit design;    applying the ATPG tools to the netlist to obtain detailed test vectors and test vector sequences for testing selected parts of the classified HDL circuit design;    combining the detailed test vectors and test vector sequences with the master template to form a complete verification test bench for the HDL circuit design; and    returning the complete verification test bench.    
     
     
         3 . The method as set forth in  claim 1 , wherein the step of merging the selected templates into a master template further includes modifying the selected templates by specifying parameters of the actual circuit.  
     
     
         4 . The method as set forth in  claim 3 , further including providing means permitting a circuit designer to modify the selected templates by specifying parameters of the actual circuit, and the circuit designer making the modifications.  
     
     
         5 . The method as set forth in  claim 2 , further providing means permitting a circuit designer to selectively apply the APTG tools to the netlist to obtain test vectors and vector sequences, and the circuit designer selectively applying the ATPG tools to the netlist.  
     
     
         6 . A test bench creation tool for use with an existing EDA tool, comprising: 
 means for receiving an HDL circuit design;    means permitting a user to annotate portions of the HDL circuit design to create a design classified by circuit-type;    a library of test bench HDL design templates;    means permitting the user to select test bench HDL design templates from the library corresponding to each classified circuit portion, and to modify the selected templates to include specific parameters of the HDL circuit design;    means permitting the user to merge the selected and modified test bench HDL design templates into a master file to form a functional verification test bench.    
     
     
         7 . The test bench creation tool as set forth in  claim 6 , further including: 
 a netlist defining a virtual circuit corresponding to the HDL circuit design;    a plurality of ATPG tools;    means permitting the user to selectively apply the ATPG tools to the netlist for obtaining test vectors and vector sequences;    means permitting the user to combine the test vectors and vector sequences with the functional verification test bench to form a complete verification test bench;    means for returning the complete verification test bench for use in verification testing to the circuit design.    
     
     
         8 . The test bench creation tool as set forth in  claim 6 , wherein the means permitting the user to merge the selected and modified test bench HDL design templates includes means permitting the user to edit the merged file.  
     
     
         9 . The test bench creation tool as set forth in  claim 7 , further including means permitting the user to edit the test vectors and vector sequences.  
     
     
         10 . A computer program product for use with a computer system, comprising: 
 a computer readable medium; and    means provided on the medium for directing the computer system to perform the following steps, defining a method for creating a verification test bench: 
 providing a circuit design expressed in an HDL;  
 providing a library of test bench HDL design templates, each adapted for testing a predetermined classification of a circuit-type;  
 classifying the parts of the HDL circuit design according to the predetermined circuit-types;  
 selecting library test bench HDL design templates for each classified part of the HDL circuit design;  
 merging the selected test bench HDL design templates into a single file; and  
 returning the file as a functional verification test bench.  
   
     
     
         11 . The computer program product as set forth in  claim 10 , wherein the means provided on the medium for directing the computer system to perform the steps defining a method for creating a verification test bench, further include: 
 providing a plurality of ATPG tools;    providing a virtual circuit netlist corresponding to the HDL circuit design;    applying the ATPG tools to netlist to generate detailed test vectors and test vector sequences for the virtual circuit;    combining the test vectors and vector sequences into a complete verification test bench; and    returning the complete verification test bench.    
     
     
         12 . The computer program product as set forth in  claim 10 , wherein the step of merging the selected templates into a single file further includes modifying the selected templates by specifying parameters of the actual circuit.  
     
     
         13 . The computer program product as set forth in  claim 12 , further including providing means permitting a circuit designer to modify the selected templates by specifying parameters of the actual circuit, and the circuit designer making the modifications.  
     
     
         14 . The computer program product as set forth in  claim 11 , further providing means permitting a circuit designer to selectively apply the APTG tools to the netlist to obtain test vectors and vector sequences, and the circuit designer selectively applying the ATPG tools to the netlist.  
     
     
         15 . The computer program product as set forth in  claim 10 , further including means permitting a circuit designer to edit the functional verification test bench.