Method for apparatus for tracking errors in a memory system

Abstract

A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of said detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

What we claim is:  
     
         1 . In a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, an error detection and tracking circuit comprising: 
 an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; and    a tracking unit connected to the error detection circuit to maintain an error history comprising a record of each of said detected errors.    
     
     
         2 . The memory system of  claim 1  wherein the error detection circuit corrects detected single-bit errors.  
     
     
         3 . The memory system of  claim 2  wherein the error detection circuit detects multi-bit errors.  
     
     
         4 . The memory system of  claim 1  wherein the error history includes a record of each of said detected errors over a predetermined tracking window.  
     
     
         5 . The memory system of  claim 4  wherein the tracking unit asserts an error signal when the number of errors recorded in the tracking window exceeds a predetermined threshold.  
     
     
         6 . The memory system of  claim 1  wherein said record includes the location in the memory of the word in which said error bit was detected.  
     
     
         7 . The memory system of  claim 6  wherein said record indicates the nature of said error.  
     
     
         8 . The memory system of  claim 1  wherein the tracking unit also maintains in said error history a record of each word accessed in said memory in which no error is detected.  
     
     
         9 . The memory system of  claim 8  wherein the tracking unit periodically discards the oldest of said records in said error history.  
     
     
         10 . The memory system of  claim 1  wherein the tracking unit selectively forwards said records in said error history.  
     
     
         11 . The memory system of  claim 1  further comprising: 
 a refresh controller connected to the memory to periodically refresh each word stored in the memory; and  
 wherein the tracking unit controls the refresh periodicity as a function of the error history.  
 
     
     
         12 . The memory system of  claim 1  further comprising: 
 a scrub controller connected to the memory to periodically scrub each word stored in the memory; and  
 wherein the tracking unit controls the scrub periodicity as a function of the error history.  
 
     
     
         13 . The memory system of  claim 1  wherein the memory includes a selectively enabled redundant bit; and wherein the tracking unit selectively enables said redundant bit as a function of the error history.  
     
     
         14 . The memory system of  claim 1  wherein the memory includes a selectively enabled sensor; and wherein the tracking unit selectively enables said sensor as a function of the error history.  
     
     
         15 . The memory system of  claim 1  further comprising: 
 a memory controller connected to the memory, the error detection circuit and the tracking unit, to control an access to the memory during an access cycle, at least one parameter of which is controllable; and  
 wherein the tracking unit controls said parameter as a function of the error history.  
 
     
     
         16 . The memory system of  claim 1  wherein the tracking unit selectively disables a selected portion of the memory as a function of the error history.  
     
     
         17 . An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the circuit comprising: 
 an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; and    a tracking unit connected to the error detection circuit to maintain an error history comprising a record of each of said detected errors.    
     
     
         18 . The circuit of  claim 17  wherein the memory includes a selectively enabled redundant bit; and wherein the tracking unit selectively enables said redundant bit as a function of the error history.  
     
     
         19 . The circuit of  claim 17  wherein the memory includes a selectively enabled sensor; and wherein the tracking unit selectively enables said sensor as a function of the error history.  
     
     
         20 . The circuit of  claim 17  further comprising: 
 a memory controller connected to the memory, the error detection circuit and the tracking unit, to control an access to the memory during an access cycle, at least one parameter of which is controllable; and  
 wherein the tracking unit controls said parameter as a function of the error history.  
 
     
     
         21 . The circuit of  claim 17  wherein the tracking unit selectively disables a selected portion of the memory as a function of the error history.  
     
     
         22 . A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: 
 detecting an error in a bit of a word accessed in the memory; and    maintaining an error history comprising a record of each of said detected errors.    
     
     
         23 . The method of  claim 22  further comprising the step of: 
 selectively enabling a redundant bit in said memory as a function of the error history.  
 
     
     
         24 . The method of  claim 22  further comprising the step of: 
 selectively enabling a sensor as a function of the error history.  
 
     
     
         25 . The method of  claim 22  further comprising the step of: 
 selectively controlling a parameter of an access cycle to the memory as a function of the error history.