DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherentmemory spaces

Abstract

In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.

I claim:  
     
         1 . A computer system, comprising: 
 an agent, a DMA controller and a memory controller, each provided in communication with a bus, the DMA controller and the memory controller provided in communication with each other via a second communication path; and    a memory, provided in communication with the memory controller, the memory having a coherent memory space and a non-coherent memory space;    wherein the DMA controller transfers a portion of data from the coherent memory space to the non-coherent memory space and transfers a portion of data from the non-coherent space to the coherent memory space with a single transaction on the external bus.    
     
     
         2 . The computer system of  claim 1 , wherein the portion of data is a cache line.  
     
     
         3 . The computer system of  claim 1 , further comprising a coherency-tracking unit that monitors read requests while the DMA controller transfers the portions of data and, if a read request references the portion of data, invalidates copies of the data with the agent after the DMA controller completes the transfers.  
     
     
         4 . A computer system, comprising: 
 a memory having coherent and non-coherent memory spaces;    a plurality of agents provided in communication via a bus that transfer data among one other via transactions on the bus, wherein: 
 one of the agents is a memory controller that bridges the memory and the bus, and  
 another of the agents is a DMA controller adapted to execute data transfers in the memory; and  
   a coherency-tracking unit that identifies read requests on the bus that are directed to the addresses of page transfers in progress and generates invalidate commands on the bus when the page transfer completes.    
     
     
         5 . The computer system of  claim 4 , wherein the DMA controller executes a data transfer with a single transaction on the external bus.  
     
     
         6 . The computer system of  claim 5  wherein the data transfer is a cache line transfer.  
     
     
         7 . A method of transferring pages of data among coherent and non-coherent memory spaces in a computer system, comprising: 
 reading first data from a coherent memory space via a bus,    reading second data from a non-coherent memory space via a secondary communication path,    writing the second data to the coherent memory space via the secondary communication path,    writing the first data to the non-coherent memory space via the secondary communication path,    between the first reading step and prior to the second writing step, determining whether there have been reads to the coherent memory space from other agents,    after the second writing step, invalidating any reads from the other agents to the coherent memory space.    
     
     
         8 . The method of  claim 7 , further comprising, a step of monitoring the bus for read requests to the coherent memory space and, if a read request references addresses of the first data, generating an invalidate command on the bus after the conclusion of the writing steps.  
     
     
         9 . The method of  claim 7 , wherein the reading and writing steps are performed on a cache-line by cache-line basis.  
     
     
         10 . A method of transferring pages of data among coherent and non-coherent memory spaces in a computer system, comprising: 
 reading first data at the coherent memory space, wherein the reading of the first data is globally observed,    reading second data from the non-coherent memory space,    writing the first data to the non-coherent memory space, and    writing the second data to the coherent memory space,    wherein the reading of the second data and the two writing steps are not globally observed,    determining whether there have been reads to the coherent memory space from other agents prior to global observation, and    after the second writing step, invalidating any detected reads from the other agents.    
     
     
         11 . The method of  claim 10 , wherein the first data is read from the coherent memory space.  
     
     
         12 . The method of  claim 10 , wherein the first data is read from another agent via a writeback.  
     
     
         13 . A method of maintaining data coherency during a data transfer operation, comprising: 
 identifying a range of addresses subject to the data transfer operation,    during the data transfer operation: 
 monitoring a bus for read requests that are not part of the data transfer operation, and  
 if any of the monitored read requests implicate an address within the range of addresses, marking the address as stale,  
   after the data transfer operation, for each stale address, generating an invalidate instruction identifying the stale address.    
     
     
         14 . The method of  claim 13 , wherein the data transfer operation comprises: 
 reading first data from the coherent memory space, wherein the reading of the first data is globally observed,    reading second data from the non-coherent memory space via a secondary communication path,    writing the first data to the non-coherent memory space via the secondary communication path, and    writing the second data to the coherent memory space via the secondary communication path,    wherein the reading of the second data and the two writing steps are not globally observed.    
     
     
         15 . A method of maintaining data coherency during a data transfer operation, comprising: 
 identifying a range of addresses subject to the data transfer operation,    during the data transfer operation: 
 monitoring a bus for a first read request of data pursuant to the data transfer operation,  
 marking an address associated with the read request as pending,  
 monitoring an external bus for read requests that are not part of the data transfer operation,  
 if any of the monitored read requests implicate an address that has been marked as pending, marking the address as stale,  
 when the data transfer associated with the first read request concludes, clearing the pending status of the address associated with the first read request,  
   after the data transfer operation, for each stale address, generating an invalidate instruction identifying the stale address.    
     
     
         16 . A coherency tracking unit, comprising: 
 a control block,    a collision detector in communication with the control block,    a stale line register in communication with the collision detector, and    an invalidate generator in communication with the control block and the stale line register.