US2003134526A1PendingUtilityA1

Chip test device used for testing a chip packaged by ball grid array (BGA) technology

Priority: Jan 15, 2002Filed: Dec 12, 2002Published: Jul 17, 2003
Est. expiryJan 15, 2022(expired)· nominal 20-yr term from priority
H01R 13/2421G01R 1/06722G01R 1/0466H01R 2201/20
24
PatentIndex Score
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Cited by
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References
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Claims

Abstract

A chip test device is provided for using a printed circuit board to perform a test process. The printed circuit board includes a pin probe socket having a plurality of pin probe holes. A chip to be tested includes a plurality of protruding electrodes. The chip test device comprises a test base for electrically coupled to the chip to be tested, a plurality of elastic first pin probes, and a test converting board having a first layer with a plurality of pin probe holes coupled to a corresponding one of the protruding electrodes and a second layer with a plurality of second pin probes coupled to a corresponding one of pin probes on the printed circuit board.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A chip test device, using a printed circuit board to perform a test process, wherein the printed circuit board includes a pin probe socket having a plurality of pin probe holes, and a chip to be tested includes a plurality of protruding electrodes, the chip test device comprising of: 
 a test base for electrically coupled to the chip to be tested;    a plurality of elastic first pin probes; and    a test converting board, having a first layer with a plurality of pin probe holes coupled to a corresponding one of the protruding electrodes, and a second layer with a plurality of second pin probes coupled to a corresponding one of pin probes on the printed circuit board.    
     
     
         2 . The chip test device as recited in  claim 1 , wherein the second pin probes are affixed to the test converting board by a manner of surface mount technology (SMT).  
     
     
         3 . The chip test device as recited in  claim 1 , wherein the test converting board is composed of six substrate layers.  
     
     
         4 . The chip test device as recited in  claim 1 , wherein the chip to be tested is packaged by using a technology of ball grid array (BGA).  
     
     
         5 . The chip test device as recited in  claim 1 , wherein the printed circuit board is a main board.  
     
     
         6 . The chip test device as recited in  claim 1 , wherein the pin probe socket includes a type of socket  370 .  
     
     
         7 . A test converting board with a top surface and a bottom surface for electrically coupling a chip to be tested with a pin probe socket, comprising of: 
 a plurality of first pin probe holes in the top surface coupled to a corresponding protruding electrode of the chip to be tested,    at least one substrate layer for electrically coupling corresponding the first pin holes in the top surface with the bottom surface; and    a plurality of second pin probes in the bottom surface coupled to a corresponding one of pin probes on the pin probe socket.    
     
     
         8 . The test converting board as recited in  claim 7 , wherein the second pin probes are affixed to the test converting board by a manner of surface mount technology (SMT).  
     
     
         9 . The test converting board as recited in  claim 7 , wherein the test converting board is composed of six substrate layers.  
     
     
         10 . The test converting board as recited in  claim 7 , wherein the chip to be tested is packaged by using a technology of ball grid array (BGA).  
     
     
         11 . The test converting board as recited in  claim 7 , wherein the pin probe socket includes a type of socket  370 .  
     
     
         12 . A test converting board with a top surface and a bottom surface for electrically coupling a BGA packaged chip to be tested with a pin probe socket, comprising of: 
 a plurality of first pin probe holes in the top surface coupled to a corresponding protruding electrode of the BGA packaged chip to be tested;    at least one substrate layer for electrically coupling corresponding the first pin holes in the top surface with the bottom surface; and    a plurality of second pin probes in the bottom surface coupled to a corresponding one of pin probes on the pin probe socket.

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