Layer structure having contact hole, fin-shaped capacitor using the layer structure, method of producing the fin-shaped capacitor, and dynamic random access memory having the fin-shaped capacitor

Abstract

A method of forming a structure having a contact hole includes the steps of (a) forming an insulating layer on a first conductive layer, (b) forming a second conductive layer on the insulating layer, (c) forming an opening in the second conductive layer, (d) forming a conductive sidewall around an inner wall of the first conductive layer defining the opening, (e) selectively etching the insulating layer in a state where the second conductive layer and the conductive sidewall function as etching masks, so that the contact hole having a width smaller than that of the opening and defined by the conductive sidewall is formed, and the first conductive layer is exposed through the contact hole, and (f) removing the second conductive layer and the conductive sidewall.

What is claimed is:  
     
         1 . A method of forming a structure having a contact hole comprising the steps of: 
 (a) forming an insulating layer on a first conductive layer;    (b) forming a second conductive layer on said insulating layer;    (c) forming an opening in said second conductive layer;    (d) forming a conductive sidewall around an inner wall of said first conductive layer defining said opening;    (e) selectively etching said insulating layer in a state where said second conductive layer and said conductive sidewall function as etching masks, so that said contact hole having a width smaller than that of said opening and defined by said conductive sidewall is formed, and said first conductive layer is exposed through said contact hole; and    (f) removing said second conductive layer and said conductive sidewall.    
     
     
         2 . A method as claimed in  claim 1 , wherein said methd comprises, between said step (e) and said step (f), the steps of: 
 (e-1) forming an etching resist on said first conductive layer exposed through said contact hole, said second conductive layer and said conductive sidewall; and    (e-2) removing only a part of said etching resist on said second conductive layer and said conductive sidewall so that said first conductive layer exposed through said contact hole is protected by said etching resist.    
     
     
         3 . A method as claimed in  claim 2 , wherein said step (e-2) comprises: 
 projecting light onto said etching resist; and    developing said etching resist so that a part of said etching resist is left on said first conductive layer exposed through said contact hole.    
     
     
         4 . A method as claimed in  claim 1 , wherein: 
 said method further comprises the step of forming an etching stopper layer on said second conductive layer; and    said etching stopper layer protects said second conductive layer during said step (d), so that the thickness of said second conductive layer can be prevented from being reduced during said step (d).    
     
     
         5 . A method as claimed in  claim 1 , wherein said method further comprises the step of forming a third conductive layer on said insulating layer and in contact with said first conductive layer exposed through said contact hole.  
     
     
         6 . A method as claimed in  claim 1 , wherein said first conductive layer comprises polysilicon.  
     
     
         7 . A method as claimed in  claim 1 , wherein: 
 said second conductive layer comprises polysilicon; and    said conductive sidewall comprises polysilicon.    
     
     
         8 . A method as claimed in  claim 1 , wherein said method further comprises the step of heating said insulating layer so that said insulating layer is reflown and an edge portion of said insulating layer defining an upper portion of said contact hole is gradually curved.  
     
     
         9 . A method of forming a structure having a contact hole comprising the steps of: 
 (a) forming an insulating layer on a first conductive layer;    (b) forming a second conductive layer on said insulating layer;    (c) forming an opening in said second conductive layer;    (d) forming a conductive sidewall around an inner wall of said first conductive layer defining said opening;    (e) selectively etching said insulating layer in a state where said second conductive layer and said conductive sidewall function as etching masks, so that said contact hole having a width smaller than that of said opening and defined by said conductive sidewall is formed on said insulating layer and said first conductive layer is exposed through said contact hole;    (f) forming a barrier layer on said second conductive layer, said conductive sidewall and said first conductive layer exposed through said contact hole; and    (g) forming a third conductive layer on said barrier layer, said barrier layer preventing said third conductive layer from reacting with said second conductive layer and said conductive sidewall.    
     
     
         10 . A method as claimed in  claim 9 , wherein: 
 said barrier layer comprises a bilayer structure having a titanium layer and a titanium nitride layer; and    said third conductive layer comprises aluminum.    
     
     
         11 . A method as claimed in  claim 9 , wherein: 
 said second conductive layer comprises polysilicon; and    said conductive sidewall comprises polysilicon.    
     
     
         12 . A method of forming a structure having a contact hole comprising the steps of: 
 (a) forming an insulating layer on a first conductive layer;    (b) forming a second conductive layer on said insulating layer;    (c) forming an opening in said second conductive layer;    (d) forming a conductive sidewall around an inner wall of said first conductive layer defining said opening;    (e) selectively etching said insulating layer in a state where said second conductive layer and said conductive sidewall function as etching masks, so that said contact hole having a width smaller than that of said opening and defined by said conductive sidewall is formed, and said first conductive layer is exposed through said contact hole; and    (f) forming a third conductive layer on said second conductive layer, said conductive sidewall and said member exposed through said contact hole,    wherein: 
 said second conductive layer comprises polysilicon;  
 said conductive sidewall comprises polysilicon; and  
 said third conductive layer comprises tungsten.  
   
     
     
         13 . A method as claimed in  claim 12 , wherein said contact hole is filled with tungsten of said third conductive layer.  
     
     
         14 . A method of forming a structure having a contact hole comprising the steps of: 
 (a) forming an insulating layer on a first conductive layer;    (b) forming a second conductive layer on said insulating layer;    (c) forming a first opening in said second conductive layer;    (d) selectively growing a third conductive layer on said second conductive layer and an inner wall of said second conductive layer defining said first opening, so that a second opening defined by said third conductive layer and having a width smaller than that of said first opening is formed; and    (e) selectively etching said insulating layer in a state where said third conductive layer functions as an etching mask, so that said contact hole having a width substantially identical to said second opening defined by said third conductive layer is formed, and said first conductive layer is exposed through said contact hole.    
     
     
         15 . A method as claimed in  claim 14 , wherein: 
 said second conductive layer comprises polysilicon; and    said third conductive layer comprises polysilicon.    
     
     
         16 . A method as claimed in  claim 14 , wherein said method further comprises the steps of: 
 forming a barrier layer on said third conductive layer and said first conductive layer exposed through said contact hole; and    forming a fourth conductive layer on said barrier layer, said barrier layer preventing said third conductive layer from reacting with said fourth conductive layer.    
     
     
         17 . A layer structure comprising: 
 a first conductive layer;    an insulating layer formed on said first conductive layer and having a contact hole, said first conductive layer being exposed through said contact hole;    a second conductive layer formed on said insulating layer and having an opening having a width larger than that of said contact hole;    a conductive sidewall formed on said insulating layer exposed through said opening and formed around an inner wall of said second conductive layer defining said opening, said conductive sidewall having a width substantially equal to that of said contact hole;    a barrier layer formed on said second conductive layer, said conductive sidewall and said first conductive layer exposed through said contact hole; and    a third conductive layer formed on said barrier layer, said barrier layer preventing said third conductive layer from reacting with said second conductive layer and said conductive sidewall.    
     
     
         18 . A layer structure as claimed in  claim 17 , wherein: 
 said third conductive layer comprises aluminum;    said first and second conductive layers comprise polysilicon; and    said conductive sidewall comprises polysilicon.    
     
     
         19 . A layer structure as claimed in  claim 17 , wherein said barrier layer comprises a bilayer structure having a titanium layer and a titanium nitride layer.  
     
     
         20 . A layer structure comprising: 
 a first conductive layer;    an insulating layer formed on said first conductive layer and having a contact hole, said first conductive layer being exposed through said contact hole;    a second conductive layer formed on said insulating layer and having a first opening having a width larger than that of said contact hole;    a third conductive layer formed on said insulating layer exposed through said first opening and said second conductive layer and formed around an inner wall of said second conductive layer defining said first opening, said third conductive layer defining a second opening having a width substantially equal to that of said contact hole, said second opening being continuously connected to said contact hole;    a barrier layer formed on said third conductive layer and said first conductive layer exposed through said contact hole; and    a fourth conductive layer formed on said barrier layer, said barrier layer preventing said fourth conductive layer from reacting with said third conductive layer and said conductive sidewall.    
     
     
         21 . A layer structure as claimed in  claim 20 , wherein: 
 said fourth conductive layer comprises aluminum; and    said first, second and third conductive layers comprise polysilicon.    
     
     
         22 . A layer structure as claimed in  claim 20 , wherein said barrier layer comprises a bilayer structure having a titanium layer and a titanium nitride layer.  
     
     
         23 . A layer structure comprising: 
 a first conductive layer;    an insulating layer formed on said first conductive layer and having a contact hole, said first conductive layer being exposed through said contact hole;    a second conductive layer formed on said insulating layer and having an opening having a width larger than that of said contact hole;    a conductive sidewall formed on said insulating layer exposed through said opening and formed around an inner wall of said second conductive layer defining said opening, said conductive sidewall having a width substantially equal to that of said contact hole; and    a third conductive layer formed on said second conductive layer, said conductive sidewall and said first conductive layer exposed through said contact hole,    wherein said third conductive layer comprises a material which causes no reaction with said second conductive layer and said conductive sidewall.    
     
     
         24 . A layer structure as claimed in  claim 23 , wherein: 
 said third conductive layer comprises tungsten;    said second conductive layer comprises polysilicon; and    said conductive sidewall comprises polysilicon.    
     
     
         25 . A dynamic random access memory comprising: 
 a semiconductor substrate having a first diffusion region and a second diffusion region of a transfer transistor;    a first insulating layer having a first contact hole exposing said first diffusion region, and a second contact hole exposing said second diffusion region;    a word line covered by said first insulating layer;    a stacked capacitor which is in contact with said first diffusion region through said first contact hole;    a bit line which is in contact with said second diffusion region through said second contact hole; and    a second insulating layer covering said stacked capacitor,    wherein: 
 said stacked capacitor comprises a storage electrode, a dielectric film and a cell plate;  
 said storage electrode which is in contact with said first diffusion region through said first contact hole has a first fin having a first portion, a second portion and a third portion;  
 said first portion has a first opening having a width greater than that of said first contact hole;  
 said second portion serving as a sidewall is formed around an inner wall of said first portion defining said first opening, so that a second opening has a width substantially identical to that of said first contact hole; and  
 said third portion extends on said first and second portions, substantially vertically extends in said first contact hole, and is in contact with said first diffusion region.  
   
     
     
         26 . A dynamic random access memory as claimed in  claim 25 , wherein: 
 said storage electrode comprises a second fin having a contact area in which said second fin is in contact with said first fin;    said contact area is wider than said first contact hole; and    said first and second fins are spaced apart from each other.    
     
     
         27 . A dynamic random access memory as claimed in  claim 25 , wherein said first fin is spaced apart from said first insulating layer.  
     
     
         28 . A dynamic random access memory as claimed in  claim 25 , wherein said first fin of said storage electrode is formed on said first insulating layer.  
     
     
         29 . A dynamic random access memory as claimed in  claim 26 , wherein said first fin of said storage electrode is thicker than said third portion thereof.  
     
     
         30 . A dynamic random access memory as claimed in  claim 25 , wherein said storage electrode having said first fin having said first, second and third portions comprises polysilicon.  
     
     
         31 . A dynamic random access memory comprising: 
 a semiconductor substrate having a first diffusion region and a second diffusion region of a transfer transistor;    a first insulating layer having a first contact hole exposing said first diffusion region, and a second contact hole exposing said second diffusion region;    a word line covered by said first insulating layer;    a stacked capacitor which is in contact with said first diffusion region through said first contact hole;    a bit line which is in contact with said second diffusion region through said second contact hole; and    a second insulating layer covering said stacked capacitor,    wherein: 
 said stacked capacitor comprises a storage electrode, a dielectric film and a cell plate; and  
 said storage electrode which is in contact with said first diffusion region through said first contact hole has a plurality of first fin-shaped portions located outside of said first contact hole, a second portion connecting said first fin-shaped portions to each other, and a third portion extending on an uppermost one of said first fin-shaped portions and said second portion, substantially vertically extending in said first contact hole, and being in contact with said first diffusion region.  
   
     
     
         32 . A dynamic random access memory as claimed in  claim 31 , wherein: 
 said second portion of said storage electrode is spaced apart from said first insulating layer; and    a lowermost one of said first fin-shaped portions of said storage electrode is spaced apart from said first insulating layer.    
     
     
         33 . A dynamic random access memory as claimed in  claim 31 , wherein: 
 said second portion of said storage electrode is in contact with said first insulating layer; and    a lowermost one of said first fin-shaped portions of said storage electrode is spaced apart from said first insulating layer.    
     
     
         34 . A dynamic random access memory as claimed in  claim 33 , wherein said storage electrode has a substantially flat surface which extends above said word line.  
     
     
         35 . A dynamic random access memory as claimed in  claim 31 , wherein said storage electrode comprises polysilicon.  
     
     
         36 . A dynamic random access memory comprising: 
 a semiconductor substrate having a first diffusion region and a second diffusion region of a transfer transistor;    a first insulating layer having a first contact hole exposing said first diffusion region, and a second contact hole exposing said second diffusion region;    a word line covered by said first insulating layer;    a stacked capacitor which is in contact with said first diffusion region through said first contact hole;    a bit line which is in contact with said second diffusion region through said second contact hole; and    a second insulating layer covering said stacked capacitor,    wherein: 
 said stacked capacitor comprises a storage electrode, a dielectric film and a cell plate; and  
 said storage electrode which is in contact with said first diffusion region through said first contact hole has a plurality of first fin-shaped portions located outside of said first contact hole, and a second portion connecting said first fin-shaped portions to each other, and extending on an uppermost one of said first fin-shaped portions, said second portion substantially vertically extending in said first contact hole, and being in contact with said first diffusion region.  
   
     
     
         37 . A dynamic random access memory as claimed in  claim 36 , wherein a lowermost one of said first fin-shaped portions is spaced apart from said first insulating layer.  
     
     
         38 . A dynamic random access memory device as claimed in  claim 36 , wherein a lowermost one of said first fin-shaped portions is in contact with said first insulating layer.  
     
     
         39 . A dynamic random access memory as claimed in  claim 36 , wherein said storage electrode comprises polysilicon.  
     
     
         40 . A fin-shaped capacitor comprising: a storage electrode having an exposed surface; 
 a dielectric film formed around said exposed surface of said storage electrode; and    a cell plate covering said storage electrode surrounded by said dielectric film,    wherein: 
 said storage electrode is in contact with a diffusion region of a semiconductor substrate through a contact hole formed in an insulating layer formed on said semiconductor substrate;  
 said storage electrode has a first fin having a first portion, a second portion and a third portion;  
 said first portion has a first opening having a width greater than that of said contact hole;  
 said second portion is formed around an inner wall of said first portion defining said first opening, so that a second opening has a width substantially identical to that of said contact hole; and  
 said third portion extends on said first and second portions, substantially vertically extends in said contact hole, and is in contact with said diffusion region in said semiconductor substrate.  
   
     
     
         41 . A fin-shaped capacitor as claimed in  claim 40 , wherein: 
 said storage electrode comprises a second fin having a contact area in which said second fin is in contact with said first fin;    said contact area is wider than said contact hole; and    said first and second fins are spaced apart from each other.    
     
     
         42 . A fin-shaped capacitor as claimed in  claim 40 , wherein said first fin is spaced apart from said insulating layer.  
     
     
         43 . A fin-shaped capacitor as claimed in  claim 40 , wherein said first fin of said storage electrode is formed on said insulating layer.  
     
     
         44 . A fin-shaped capacitor as claimed in  claim 41 , wherein said first fin of said storage electrode is thicker than said third portion thereof.  
     
     
         45 . A fin-shaped capacitor as claimed in  claim 40 , wherein said storage electrode having said first fin having said first, second and third portions comprises polysilicon.  
     
     
         46 . A fin-shaped capacitor comprising: 
 a storage electrode having an exposed surface;    a dielectric film formed around said exposed surface of said storage electrode; and    a cell plate covering said storage electrode surrounded by said storage electrde,    wherein: 
 said storage electrode is in contact with a diffusion region of a semiconductor substrate through a contact hole formed in an insulating layer formed on said semiconductor substrate;  
 said storage electrode has a plurality of first fin-shaped portions located outside of said contact hole, a second portion connecting said first fin-shaped portions to each other, and a third portion extending on an uppermost one of said first fin-shaped portions and said second portion, substantially vertically extending in said contact hole, and being in contact with said diffusion region of said semiconductor substrate.  
   
     
     
         47 . A fin-shaped capacitor as claimed in  claim 46 , wherein: 
 said second portion of said storage electrode is spaced apart from said insulating layer; and    a lowermost one of said first fin-shaped portions of said storage electrode is spaced apart from said insulating layer.    
     
     
         48 . A fin-shaped capacitor as claimed in  claim 46 , wherein: 
 said second portion of said storage electrode is in contact with said insulating layer; and    a lowermost one of said first fin-shaped portions of said storage electrode is spaced apart from said insulating layer.    
     
     
         49 . A fin-shaped capacitor as claimed in  claim 48 , wherein said insulating layer has a substantially flat surface on which said second portion of said storage electrode is formed.  
     
     
         50 . A fin-shaped capacitor as claimed in  claim 46 , wherein said storage electrode comprises polysilicon.  
     
     
         51 . A fin-shaped capacitor comprising: 
 a storage electrode having an exposed surface;    a dielectric film formed around said exposed surface of said storage electrode; and    a cell plate covering said storage electrode surrounded by said storage electrode,    wherein: 
 said storage electrode is in contact with a diffusion region of a semiconductor substrate through a contact hole formed in an insulating layer formed on said semiconductor substrate;  
 said storage electrode has a plurality of first fin-shaped portions located outside of said contact hole, and a second portion connecting said fin-shaped portions to each other, and extending on an uppermost one of said first fin-shaped portions, said second portion substantially vertically extending in said contact hole, and being in contact with said diffusion region in said semiconductor substrate.  
   
     
     
         52 . A fin-shaped capacitor as claimed in  claim 51 , wherein a lowermost one of said first fin-shaped portions is spaced apart from said insulating layer.  
     
     
         53 . A fin-shaped capacitor device as claimed in  claim 51 , wherein a lowermost one of said first fin-shaped portions is in contact with said insulating layer.  
     
     
         54 . A fin-shaped capacitor as claimed in  claim 51 , wherein said storage electrode comprises polysilicon.  
     
     
         55 . A method of producing a fin-shaped capacitor in a dynamic random access memory comprising the steps of: 
 (a) forming an insulating layer on a semiconductor substrate having a diffusion region;    (b) forming a first conductive layer having a first opening on said insulating layer;    (c) forming a conductive sidewall around an inner wall of said first conductive layer defining said first opening, said conductive sidewall defining a second opening having a width smaller than that of said first opening;    (d) selectively etching said insulating layer in a state where said first conductive layer and said conductive sidewall function as etching masks, so that said diffusion region is exposed through a contact hole formed in said insulating layer and having a width substantially identical to that of said second opening;    (e) forming a second conductive layer on said first conductive layer, said conductive sidewall and said diffusion region exposed through said contact hole;    (f) patterning said first conductive layer and said second conductive layer into a shape of a storage electrode of said fin-shaped capacitor;    (g) forming a dielectric film around an exposed surface of said storage electrode; and    (h) forming a cell plate around said storage electrode covered by said dielectric film.    
     
     
         56 . A method as claimed in  claim 55 , wherein said step (a) comprises the steps of: 
 forming a first insulating layer directly on said semiconductor substrate; and    forming a second insulating layer on said semiconductor substrate, said insulating layer having said first and second insulating layers, and    wherein said method further comprises the step of isotropically etching said second insulating layer, so that said storage electrode is spaced apart from said first insulating layer.    
     
     
         57 . A method of producing a fin-shaped capacitor in a dynamic random access memory comprising the steps of: 
 (a) forming a first insulating layer on a semiconductor substrate having a diffusion region;    (b) forming a first conductive layer having a first opening on said first insulating layer;    (c) forming a conductive sidewall around an inner wall of said first conductive layer defining said first opening, said conductive sidewall defining a second opening having a width smaller than that of said first opening;    (d) selectively etching said first insulating layer in a state where said first conductive layer and said conductive sidewall function as etching masks, so that said diffusion region is exposed through a contact hole formed in said first insulating layer and having a width substantially identical to that of said second opening;    (e) forming a second conductive layer on said first conductive layer, said conductive sidewall and said diffusion region exposed through said contact hole;    (f) forming, on said second conductive layer, a second insulating layer having a third opening having a width substantially identical to that of said first opening;    (g) forming a third conductive layer on said second insulating layer and said second conductive layer through said third opening;    (h) patterning said first and second conductive layers and said second insulating layer into a shape of a storage electrode of said fin-shaped capacitor;    (i) isotropically etching said second insulating layer so as to be removed;    (j) forming a dielectric film around an exposed surface of said storage electrode; and    (k) forming a cell plate around said storage electrode covered by said dielectric film.    
     
     
         58 . A method as claimed in  claim 57 , wherein said step (a) comprises the steps of: 
 forming a third insulating layer directly on said semiconductor substrate; and    forming a fourth insulating layer on said third insulating layer;    forming a fifth insulating layer on said fourth insulating layer, said first insulating layer has said third and fourth insulating layers, and    wherein: 
 said fifth insulating layer is formed of a material identical to that of said third insulating material; and  
 said fifth insulating layer is removed during said step (i), so that said storage electrode is spaced apart from said fourth insulating layer.  
   
     
     
         59 . A method as claimed in  claim 57 , wherein: 
 said step (h) comprises:    forming a third insulating layer having a fourth opening on said third conductive layer, said fourth opening being located at a position different from that of said first opening;    forming an insulating sidewall around an inner surface of said fourth insulating layer defining said fourth opening, said insulating sidewall defining a fifth opening having a width smaller than that of said fourth opening; and    etching said first, second and third conductive layers and said second and third insulating layers in a state where said fourth insulating layer and said insulating sidewall function as etching masks.    
     
     
         60 . A method of producing a fin-shaped capacitor in a dynamic random access memory comprising the steps of: 
 (a) forming a first insulating layer on a semiconductor substrate having a diffusion region;    (b) forming a plurality of stacked-layer structures, a lowermost one of said stacked-layer structures being formed on said first insulating layer, each of said stacked-layer structures having a spacer layer and a first conductive layer;    (c) forming a first opening in said stacked-layer structures except said spacer layer of said lowermost one of said stacked-layer structures;    (d) forming a conductive sidewall around an inner wall of said stacked-layer structures defining said first opening, said conductive sidewall defining a second opening having a width smaller than that of said first opening;    (e) selectively etching said spacer layer of the lowermost one of said stacked-layer structures and said first insulating layer in a state where said first conductive layer of an uppermost one of said stacked layer structures and said conductive sidewall function as masks, so that said diffusion region is exposed through a contact hole formed in said spacer layer of the lowermost one of said stacked-layer structures and said first insulating layer;    (f) forming a second conductive layer on said first conductive layer of the uppermost one of said stacked-layer structures, said conductive sidewall and said diffusion region exposed through said contact hole;    (g) patterning said second conductive layer and said stacked-layer structures except said spacer layer of the lowermost one of said stacked-layer structures into a shape of a storage electrode of said fin-shaped capacitor;    (h) isotropically etching said spacer layer of each of said stacked-layer structures so that said spacer layer is removed;    (i) forming a dielectric film around said storage electrode; and    (j) forming a cell plate around said storage electrode covered by said dielectric film.    
     
     
         61 . A method as claimed in  claim 60 , wherein: 
 said method further comprises, between said steps (b) and (c), the step of forming a second insulating layer on said first conductive layer of the uppermost one of said stacked-layer structures; and    said second insulating layer is removed during said step (e).    
     
     
         62 . A method as claimed in  claim 60 , wherein said step (a) comprises the steps of: 
 forming a second insulating layer on said semiconductor substrate;    forming a third insulating layer on said second insulating layer;    heating said third insulating layer so that said third insulating layer has a substantially flat surface; and    forming a fourth insulating layer on said substantially flat surface of said third insulating layer, and    wherein: 
 said second, third and fourth insulating layers form said first insulating layer.  
   
     
     
         63 . A method as claimed in  claim 60 , wherein: 
 said first conductive layer comprises polysilicon; and    said spacer layer comprises silicon oxide.    
     
     
         64 . A method as claimed in  claim 62 , wherein: 
 said second and fourth insulating layers comprises silicon oxide; and    said third insulating layer comprises one of a spin-on-glass layer and a phosphosilicate glass layer.    
     
     
         65 . A method of producing a fin-shaped capacitor in a dynamic random access memory comprising the steps of: 
 (a) forming a first insulating layer on a semiconductor substrate having a diffusion region;    (b) forming a plurality of stacked-layer structures, a lowermost one of said stacked-layer structures being formed on said first insulating layer, each of said stacked-layer structures having a spacer layer and a first conductive layer;    (c) forming a first opening in said stacked-layer structures;    (d) forming a conductive sidewall around an inner wall of said stacked-layer structures defining said first opening, said conductive sidewall defining a second opening having a width smaller than that of said first opening;    (e) selectively etching said first insulating layer in a state where said first conductive layer of an uppermost one of said stacked layer structures and said conductive sidewall function as masks, so that said diffusion region is exposed through a contact hole formed in said first insulating layer;    (f) forming a second conductive layer on said first conductive layer of the uppermost one of said stacked-layer structures, said conductive sidewall and said diffusion region exposed through said contact hole;    (g) patterning said second conductive layer and said stacked-layer structures into a shape of a storage electrode of said fin-shaped capacitor;    (h) isotropically etching said spacer layer of each of said stacked-layer structures so that said spacer layer is removed;    (i) forming a dielectric film around said storage electrode; and    (j) forming a cell plate around said storage electrode covered by said dielectric film.    
     
     
         66 . A method as claimed in  claim 65 , wherein: 
 said method further comprises, between said steps (b) and (c), the step of forming a second insulating layer on said first conductive layer of the uppermost one of said stacked-layer structures; and    said second insulating layer is removed during said step (e).    
     
     
         67 . A method as claimed in  claim 65 , wherein said step (a) comprises the steps of: 
 forming a second insulating layer on said semiconductor substrate;    forming a third insulating layer on said second insulating layer;    heating said third insulating layer so that said third insulating layer has a substantially flat surface; and    forming a fourth insulating layer on said substantially flat surface of said third insulating layer, and    wherein: 
 said second, third and fourth insulating layers form said first insulating layer.  
   
     
     
         68 . A method as claimed in  claim 65 , wherein: 
 said first conductive layer comprises polysilicon; and    said spacer layer comprises silicon oxide.    
     
     
         69 . A method as claimed in  claim 67 , wherein: 
 said second and fourth insulating layers comprise silicon oxide; and    said third insulating layer comprises one of a spin-on-glass layer and a phosphosilicate glass layer.    
     
     
         70 . A method of producing a fin-shaped capacitor in a dynamic random access memory comprising the steps of: 
 (a) forming a first insulating layer on a semiconductor substrate having a diffusion region;    (b) forming a plurality of stacked-layer structures, a lowermost one of said stacked-layer structures being formed on said first insulating layer, each of said stacked-layer structures having a spacer layer and a first conductive layer;    (c) forming a contact hole in said stacked-layer structures and said first insulating layer so that said diffusion layer is exposed through said contact hole;    (d) forming a second conductive layer on said first conductive layer of an uppermost one of said stacked-layer structure and said diffusion layer exposed through said contact hole, said second conductive layer substantially vertically extending along an inner wall of said contact hole;    (e) patterning said second conductive layer and said stacked-layer structures into a shape of a storage electrode of said fin-shaped capacitor;    (f) isotropically etching said spacer layer of each of said stacked-layer structures so that said spacer layer is removed;    (i) forming a dielectric film around said storage electrode; and    (j) forming a cell plate around said storage electrode covered by said dielectric film.    
     
     
         71 . A method as claimed in  claim 70 , wherein said step (a) comprises the steps of: 
 forming a second insulating layer on said semiconductor substrate;    forming a third insulating layer on said second insulating layer;    heating said third insulating layer so that said third insulating layer has a substantially flat surface; and    forming a fourth insulating layer on said substantially flat surface of said third insulating layer, and    wherein: 
 said fourth insulating layer is removed during said step (f).  
   
     
     
         72 . A method as claimed in  claim 71 , wherein: 
 said second and fourth insulating layers comprises silicon oxide;    said third insulating layer comprises silicon nitride; and    said first and second conductive layers comprise polysilicon.    
     
     
         73 . A method as claimed in  claim 70 , wherein: 
 said step (c) comprises: 
 forming a third conductive layer on a top of said stacked layer structures;  
 forming a second insulating layer on said third conductive layer;  
 forming a photoresist film having a window pattern on said second insulating layer;  
 etching said second insulating layer and said third conductive layer so that a first window is formed in said third conductive layer and said second insulating layer;  
 removing said photoresist film; and  
 forming a conductive sidwall around an inner wall of said third conductor layer defining said window,  
 wherein said contact hole formed by said step (c) having a size defined by said conductive sidewall.