Ball grid substrate for lead-on-chip semiconductor package

Abstract

A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.

1 . A package substrate suitable for use with a ball grid array, comprising: 
 an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces of the heat sink;    a dielectric layer formed directly on the bottom surface of the heat sink proximate the slot;    a circuit disposed on the dielectric layer, the circuit electrolytically and selectively formed in a circuit pattern; and    an electrically resistive soldermask disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit.    
     
     
         2 . The package substrate of  claim 1 , further comprising a via filled with a heat conducting material, which via extends through the dielectric layer and is accessible through the soldermask.  
     
     
         3 . The package substrate of  claim 1 , further comprising a layer of an adhesive secured to the top surface of the heat sink proximate the slot in a manner effective to adhere an integrated circuit die thereto.  
     
     
         4 . The package substrate of  claim 1 , wherein the bond pads comprise: 
 a row of spaced wire bond pads formed adjacent a side edge of the slot and exposed through the openings in the soldermask, which wire bond pads are suitable for connection by wires to corresponding wire bond pads of an integrated circuit disposed over the slot on the top surface of the heat sink; and    a row of spaced terminal pads that is remote from the wire bond pads and slot edge, the circuit pattern including lines which connect each wire bond pad to its corresponding terminal pad.    
     
     
         5 . The package substrate of  claim 6 , further comprising 
 a via filled with a heat conducting material, which via extends through the dielectric layer and is accessible through the soldermask; and    a layer of an adhesive secured to the top surface of the heat sink proximate the slot in a manner effective to adhere an integrated circuit die thereto.    
     
     
         6 . The package substrate of  claim 1 , further comprising: 
 a layer of an adhesive secured to the top surface of the heat sink proximate the slot;    an integrated circuit die attached to the top surface of the heat sink by the adhesive layer on opposite sides of the slot, such that wire bond pads on the die are exposed in the slot;    electrically conductive wires bonded to the wire bond pads on the die and to wire bond pads of the circuit adjacent the slot;    an encapsulant covering the wires and the die; and    solder balls bonded to ball pads of the circuit.    
     
     
         7 . The package substrate of  claim 6 , further comprising a via filled with a heat conducting material, which via extends through the dielectric layer and is accessible through the soldermask.  
     
     
         8 . The package substrate of  claim 6 , wherein the bond pads comprise: 
 a row of spaced wire bond pads formed adjacent a side edge of the slot and exposed through the openings in the soldermask, which wire bond pads are suitable for connection by wires to corresponding wire bond pads of an integrated circuit disposed over the slot on the top surface of the heat sink; and    a row of spaced terminal pads that is remote from the wire bond pads and slot edge, the circuit pattern including lines which connect each wire bond pad to its corresponding terminal pad.    
     
     
         9 . The package substrate of  claim 1 , wherein the heat sink consists essentially of copper.  
     
     
         10 . The package substrate of  claim 1 , further comprising 
 a second dielectric layer formed on the circuit;    a second circuit disposed-on the second dielectric layer, the second circuit electrolytically and selectively formed in a second circuit pattern; and    an electrically resistive soldermask disposed on the dielectric layers and the circuits, which soldermask has openings therethrough which expose bond pads of the circuits.    
     
     
         11 . The package substrate of  claim 1 , wherein only one circuit and one dielectric layer are included, such that the soldermask is formed directly over the circuit.  
     
     
         12 . A lead frame, comprising a strip of package substrates as claimed in  claim 1  formed side by side and connected on the ends by rails.  
     
     
         13 . The lead frame of  claim 12 , wherein each package substrate is separated from each adjacent package substrate by an elongated widthwise slot having a greater length than the slot in the heat sink.  
     
     
         14 . An integrated circuit and package substrate suitable for use with a ball grid array, comprising: 
 an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces of the heat sink;    a dielectric layer formed directly on the bottom surface of the heat sink proximate the slot;    a circuit disposed on the dielectric layer, the circuit electrolytically and selectively formed in a circuit pattern; and    an electrically resistive soldermask disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit;    a via filled with a heat conducting material, which via extends through the dielectric layer and is accessible through the soldermask. and    an integrated circuit die attached to the top surface of the heat sink by an adhesive such that wire bond pads on the die are exposed in the slot.    
     
     
         15 . The integrated circuit and package substrate of  claim 14  wherein the via is formed directly on the electrically and thermally conductive heat sink and extends from the electrically and thermally conductive heat sink through the dielectric layer.  
     
     
         16 . The integrated circuit package of  claim 14  further comprising a plurality of vias extending from the electrically and thermally conductive heat sink through the dielectric layer.