Non-volatile memory and fabrication thereof

Abstract

A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step. The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

What is claimed is:  
     
         1 . A method for fabricating a non-volatile memory, comprising the steps of: 
 forming a planar doped region in a substrate;    forming a mask layer and a patterned photoresist layer on the substrate;    forming a plurality of trenches in the substrate by patterning the mask layer and the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of buried bit-lines;    removing the patterned photoresist layer;    removing the mask layer;    forming a dielectric layer on the substrate; and    forming a plurality of word-lines on the dielectric layer.    
     
     
         2 . The method of  claim 1 , further comprising performing a recovering process to recover side-walls and bottoms of the trenches from damages caused by the step of forming the trenches.  
     
     
         3 . The method of  claim 2 , wherein the recovering process comprises: 
 performing a thermal oxidation process to form a liner oxide layer on the trenches with the mask layer as a mask; and    removing the liner oxide layer.    
     
     
         4 . The method of  claim 1 , wherein the dielectric layer comprises silicon oxide.  
     
     
         5 . The method of  claim 1 , wherein the dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.  
     
     
         6 . The method of  claim 1 , wherein the mask layer comprises silicon nitride.  
     
     
         7 . The method of  claim 1 , further comprising forming a pad oxide layer on the substrate before the mask layer is formed on the substrate.  
     
     
         8 . The method of  claim 1 , wherein the method for forming the planar doped region comprises ion implantation.  
     
     
         9 . A method for fabricating a mask read-only memory (Mask ROM), comprising the steps of: 
 forming a planar doped region in a substrate;    forming a mask layer and a first patterned photoresist layer on the substrate;    forming a plurality of trenches in the substrate by patterning the mask layer and the substrate with the first patterned photoresist layer as a mask to divide the planar doped region into a plurality of buried bit-lines;    removing the first patterned photoresist layer;    removing the mask layer;    forming a gate dielectric layer on the substrate;    forming a plurality of word-lines on the gate dielectric layer, wherein one portion of a bottom of each trench covered by one word-line serves as one coding region;    forming a second patterned photoresist layer over the substrate, the second patterned photoresist layer having a plurality of openings over selected coding regions; and    performing an ion implantation with the second patterned photoresist layer as a mask to form a plurality of doped coding regions from the selected coding regions.    
     
     
         10 . The method of  claim 9 , further comprising performing a recovering process to recover side-walls and bottoms of the trenches from damages caused by the step of forming the trenches.  
     
     
         11 . The method of  claim 10 , wherein the recovering process comprises: 
 performing a thermal oxidation process to form a liner oxide layer on the trenches with the mask layer as a mask; and    removing the liner oxide layer.    
     
     
         12 . The method of  claim 9 , wherein the gate dielectric layer comprises silicon oxide.  
     
     
         13 . The method of  claim 9 , wherein the mask layer comprises silicon nitride.  
     
     
         14 . The method of  claim 9 , further comprising forming a pad oxide layer on the substrate before the mask layer is formed on the substrate.  
     
     
         15 . The method of  claim 9 , wherein the method for forming the planar doped region comprises ion implantation.  
     
     
         16 . A method for fabricating a nitride read-only memory (NROM), comprising the steps of: 
 forming a planar doped region in a substrate;    forming a mask layer and a patterned photoresist layer on the substrate;    forming a plurality of trenches in the substrate by patterning the mask layer and the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of buried bit-lines;    removing the patterned photoresist layer;    removing the mask layer;    forming a charge trapping layer on the substrate; and    forming a plurality of word-lines on the charge trapping layer.    
     
     
         17 . The method of  claim 16 , further comprising performing a recovering process to recover side-walls and bottoms of the trenches from damages caused by the step of forming the trenches.  
     
     
         18 . The method of  claim 17 , wherein the recovering process comprises: 
 performing a thermal oxidation process to form a liner oxide layer on the trenches with the mask layer as a mask; and    removing the liner oxide layer.    
     
     
         19 . The method of  claim 16 , wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.  
     
     
         20 . The method of  claim 16 , wherein the method for forming the planar doped region comprises ion implantation.  
     
     
         21 . A non-volatile memory, comprising: 
 a substrate;    a plurality of buried bit-lines in the substrate, wherein the buried bit-lines are separated by a plurality of isolating structures;    a plurality of word-lines covering a portion of the substrate and crossing over the buried bit-lines and the isolating structures; and    a dielectric layer between the substrate and the word-lines.    
     
     
         22 . The non-volatile memory of  claim 21 , wherein the dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.  
     
     
         23 . The non-volatile memory of  claim 21 , wherein the isolating structures comprise trenches.  
     
     
         24 . The non-volatile memory of  claim 21 , wherein the dielectric layer comprises a silicon oxide layer.  
     
     
         25 . The non-volatile memory of  claim 21 , wherein the word-lines comprise polysilicon or doped polysilicon.