Vertical mos transistor with buried gate and method for making same

Abstract

According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly ( 28 ) formed above the drain ( 2 ) comprises insulating zones ( 42, 44 ) either side of the drain; cavities extend under the insulating assembly, either side of the channel ( 69 ); the gate ( 77 a, 77 b ) is formed either side of this insulating assembly; and portions of the gate are located inside the cavities. The invention applies to microelectronics.

1 . Transistor of vertical MOS type comprising: 
 a semiconductor substrate ( 18 ),    a source ( 68 ) in semiconductor material formed in or on this substrate,    a channel ( 69 ) formed above the source and made in a semiconductor material of opposite doped type to the source,    a drain ( 26 ) formed above the channel and made in a semiconductor material of identical doped type to the source, and    a gate ( 77   a ,  77   b ) formed either side of the channel and drain and electrically insulated from the source, the channel and the drain,    this transistor being characterized in that it also comprises:    an electrically insulating assembly ( 28 ) formed above the drain, this electrically insulating assembly comprising electrically insulating zones ( 42 ,  44 ) either side of the drain, and    cavities ( 78 ,  80 ) which extend underneath the electrically insulating assembly, either side of the channel, the gate being formed either side of this electrically insulating assembly, portions of the gate being located inside the cavities, electrically insulating thin layers ( 70 ,  72 ) extending at least between the channel and these portions of gate and other, electrically insulating, thick layers ( 66 ,  67 ) extending between the gate and the source.    
     
     
         2 . Transistor according to  claim 1 , in which the gate ( 77   a ,  77   b ) is made in a metallic material.  
     
     
         3 . Fabrication process for a transistor of vertical MOS type according to  claim 1 , in which: 
 a structure is formed comprising a semiconductor substrate ( 18 ), a source zone ( 27 ), a channel zone ( 23 ) and the drain above the channel zone,    above the drain an electrically insulating assembly ( 28 ) is formed comprising the electrically insulating zones ( 42 ,  44 ) either side of the drain,    in this structure two recesses ( 46 ,  48 ) are formed either side of the electrically insulating assembly, the respective sidewalls ( 46   a ,  48   a ) of these recesses the closest to the electrically insulating assembly being positioned beneath the latter, either side of the channel zone, to form cavities ( 78 ,  80 ),    electrically insulating layers ( 70 ,  72 ) are formed at least on these sidewalls of the recesses, and other electrically insulating layers ( 66 ,  67 ) at the bottom of these recesses, and    the gate ( 77   a ,  77   b ) of the transistor is formed either side of the electrically insulating assembly and reaching into the cavities.    
     
     
         4 . Process according to  claim 3  in which, to form the electrically insulating assembly: 
 on the structure a first layer ( 30 ) is formed which is electrically insulating and, on this first layer, a second layer ( 32 ) which is also electrically insulating,  
 these first and second layers are etched to obtain an insulating element ( 34 ,  36 ) which covers the drain,  
 above this insulating element, a third layer ( 38 ) is formed which is also electrically insulating, and  
 this third layer is etched so as to form electrically insulating zones ( 42 ,  44 ) and to complete the formation of the electrically insulating assembly.  
 
     
     
         5 . Process according to  claim 4 , in which the second layer ( 32 ) is also able to act as planarization stop layer for a metal layer ( 77 ) which is subsequently formed and which is intended to form the gate ( 77   a ,  77   b ) of the transistor.  
     
     
         6 . Process according to any of  claims 3  to  5 , in which: 
 through the electrically insulating assembly, a hole ( 74 ) is formed which extends as far as the drain, and  
 in this hole a layer ( 77   c ) is formed which is a drain pre-contact layer.  
 
     
     
         7 . Process according to  claim 6 , in which the gate ( 77   a ,  77   b ) is formed at the same time as this drain pre-contact layer ( 77   c ).