Semiconductor integrated circuit device and method of manufacturing the same

Abstract

In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device, comprising: 
 memory cells, each memory cell being comprised of a memory cell selection MISFET and an information storage capacitive element connected in series with said memory cell selection MISFET, the memory cells including bit lines;    a first interconnection formed over said memory cell selection MISFET;    a first insulating film formed over said first interconnection;    a second insulating film formed over said information storage capacitive element;    a second interconnection formed over said second insulating film;    a first conductive layer formed within a first through hole defined in said second insulating film and said first insulating film below said second insulating film, said first conductive layer connecting said second interconnection and said first interconnection;    a third insulating film formed over said second interconnection;    a feeding interconnection for supplying a predetermined potential to an upper electrode of said information storage capacitive element formed over said third insulating film; and    a second conductive layer formed within a second through hole defined in said third insulating film and said second insulating film placed in a layer therebelow;    wherein said second conductive layer connects said upper electrode and said feeding interconnection;    wherein said first insulating film includes a plurality of grooves;    wherein a lower electrode of said information storage capacitive element is formed over an inner surface of a groove of said plurality of grooves;    wherein a dielectric film of said information storage capacitive element is formed over said lower electrode;    wherein an upper electrode is formed over said dielectric film and over said first insulating film outside said groove;    wherein said upper electrode formed over said first insulating film outside said groove is located in a first region; and    wherein said feeding interconnection and said upper electrode are connected in said first region.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein a bottom surface of said upper electrode in said first region is higher than a level of one-half of the depth of said groove.  
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein said upper electrode in said first region is formed over a top surface of said first insulating film.  
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein an aspect ratio of said first through hole is larger than that of said second through hole.  
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , further comprising a third interconnection formed over said third insulating film; and a third conductive layer formed within a third through hole defined in said third insulating film below said third interconnection, said third conductive layer connecting said third interconnection and said second interconnection, wherein said third interconnection and said feeding interconnection are formed in a same wiring layer.  
     
     
         6 . The semiconductor integrated circuit device according to  claim 5 , wherein an aspect ratio of said second through hole is larger than that of said third through hole.  
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , wherein each of said bit lines is formed in a same wiring layer as a first interconnection of a peripheral circuit of the device and is formed below the information storage capacitive elements.  
     
     
         8 . The semiconductor integrated circuit device according to  claim 2 , wherein said first and second interconnections are disposed in a peripheral circuit region.  
     
     
         9 . The semiconductor integrated circuit device according to  claim 2 , wherein the lower electrode of each information storage capacitor element is electrically connected to a source region or a drain region of a respective memory cell selection MISFET.  
     
     
         10 . The semiconductor integrated circuit device according to  claim 2 , wherein said lower electrode is a layer of conductive material extending along said side wall of said groove.  
     
     
         11 . The semiconductor integrated circuit device according to  claim 2 , wherein said lower electrode of each information storage capacitive element is in contact with said side wall of said groove.