Multi-chip stack package and fabricating method thereof

Abstract

Abstract of Disclosure A multi-chip stack package having a substrate, a first chip, a second chip, a plurality of bumps, a plurality of junction interface bumps, a plurality of conductive wires, a first filler material, a second filler material and an encapsulating material is provided. The substrate has a substrate surface with a plurality of first contacts and a plurality of second contacts. The first chip has a first active surface with a plurality of bonding pads thereon and a first chip back surface. The first chip is positioned over the substrate surface. The second chip has a second active surface with a plurality of bonding pads thereon and a second chip back surface. The second chip is positioned over the first chip back surface. The bumps are positioned between the first bonding pads and the first contacts. The junction interface bumps are positioned between the first chip back surface and the second chip back surface. The conductive wires electrically connect the second bonding pads and the second contacts. The first filler material encloses the bumps and the second filler material encloses the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.

Claims 
     
         1.  A multi-chip stack package, comprising: 
       a substrate having a substrate surface with a plurality of first contacts and a plurality of second contacts thereon; 
       a first chip having a first active surface and a corresponding first chip back surface, wherein the first chip has a plurality of first bonding pads on the first active surface and the first chip is over the substrate surfaces such that the first active surface faces the substrate surface; 
       a second chip having a second active surface and a corresponding second chip back surface, wherein the second chip has a plurality of second bonding pads on the second active surface and the second chip is over the first chip back surface such that the second chip back surface faces the first chip back surface; 
       a plurality of bumps connecting the first bonding pads and the first contacts; 
       a plurality of junction interface bumps connecting the first chip back surface and the second chip back surface; 
       a plurality of conductive wires with one end bonded to one of the second bonding pads and the other end bonded to one of the second contacts; 
       a first filler material enclosing the bumps; 
       a second filler material enclosing the junction interface bumps; and 
       an encapsulate material at least enclosing the first chip, the second chip and the conductive wires. 
     
     
         2.  The multi-chip stack package of  claim 1 , wherein the package further includes an under-bump-metallurgy layer on the first chip back surface. 
     
     
         3.  The multi-chip stack package of  claim 2 , wherein the under-bump-metallurgy layer includes a barrier layer over the first chip back surface. 
     
     
         4.  The multi-chip stack package of  claim 3 , wherein the barrier layer is fabricated using a metallic material selected from the group consisting of titanium, titanium tungsten and chromium. 
     
     
         5.  The multi-chip stack package of  claim 4 , wherein the under-bump-metallurgy layer further includes a seed layer over the barrier layer and the seed layer is fabricated using a metallic material . 
     
     
         6.  The multi-chip stack package of  claim 1 , wherein the package further includes an under-bump-metallurgy layer on the second chip back surface. 
     
     
         7.  The multi-chip stack package of  claim 6 , wherein the under-bump-metallurgy layer includes a barrier layer over the second chip back surface and the barrier layer is fabricated using a metallic material selected from the group consisting of titanium, titanium tungsten and chromium. 
     
     
         8.  The multi-chip stack package of  claim 7 , wherein the under-bump-metallurgy layer further includes a seed layer over the barrier layer. 
     
     
         9.  The multi-chip stack package of  claim 8 , wherein the seed layer is fabricated using a metallic material. 
     
     
         10.  The multi-chip stack package of  claim 1 , wherein the junction interface bumps are fabricated using a lead-tin alloy. 
     
     
         11.  A multi-chip bonded structure, at least comprising: 
       a first chip having a first chip back surface; 
       a second chip over the first chip back surface, wherein the second chip has a second chip back surface and the second chip back surface faces the first chip back surface; and 
       at least one bump between the first chip back surface and the second chip back surface. 
     
     
         12.  The multi-chip bonded structure of  claim 11 , wherein the structure further includes an under-bump-metallurgy layer on the first chip back surface. 
     
     
         13.  The multi-chip bonded structure of  claim 12 , wherein the under-bump-metallurgy layer includes a barrier layer over the first chip back surface. 
     
     
         14.   The multi-chip bonded structure of  claim 13 , wherein the barrier layer is fabricated using a metallic material selected from the group consisting of titanium, titanium tungsten and chromium. 
     
     
         15.  The multi-chip bonded structure of  claim 13 , wherein the under-bump-metallurgy layer further includes a seed layer over the barrier layer and that the seed layer is fabricated using a metallic material. 
     
     
         16.  The multi-chip bonded structure of  claim 11 , wherein the package further includes an under-bump-metallurgy layer on the second chip back surface. 
     
     
         17.  The multi-chip bonded structure of  claim 16 , wherein the under-bump-metallurgy layer includes a barrier layer  over the second chip back surface and the barrier layer is fabricated using a metallic material selected from a group consisting of titanium, titanium tungsten and chromium. 
     
     
         18.  The multi-chip bonded structure of  claim 17 , wherein the under-bump-metallurgy layer further includes a seed layer over the barrier layer. 
     
     
         19.   The multi-chip bonded structure of  claim 18 , wherein the seed layer is fabricated using a metallic material including copper. 
     
     
         20.  The multi-chip bonded structure of  claim 11 , wherein the bumps are fabricated using a lead-tin alloy. 
     
     
         21.  The multi-chip bonded structure of  claim 11 , wherein the structure further includes a filler material that encloses the bumps.