Semiconductor storage device and method of manufacturing the same

Abstract

In a memory cell area (A) of a semiconductor storage device, a capacitor ( 8 ) formed on a first insulating layer ( 5 ) formed so as to cover MOS transistors ( 3, 4 ) includes a pillar-shaped insulating member ( 8 a ), a first capacitance electrode ( 8 b ) formed on the side surface of the pillar-shaped insulating member ( 8 a ), a capacitance insulating film ( 8 c ) formed on the first capacitance electrode ( 8 b ) and a second capacitance electrode ( 8 d ) formed on the capacitance insulating film ( 8 c ). A conductive member ( 7 ) for connecting the source or drain ( 3 a ) of the MOS transistor ( 3 ) to the first capacitance electrode ( 8 b ) is filled in a connection opening ( 6 ) formed in the first insulating layer ( 5 ). In a peripheral circuit area (B) other than the memory cell area (A) containing plural memory cells each having the MOS transistor ( 3 ) and the capacitor ( 8 ), a second insulating layer ( 9 ) which is formed simultaneously with the formation of the pillar-shaped insulating member ( 8 a ) of the capacitor ( 8 ) and has the same height as the pillar-shaped insulating member ( 8 a ) is formed on the first insulating layer ( 5 ).

What is claimed is  
     
         1 . A semiconductor storage device having plural memory cells each containing a capacitor and a transistor, characterized in that a first insulating layer is formed so as to cover said transistor, said capacitor is formed on said first insulating layer, said capacitor contains a pillar-shaped insulating member formed on said first insulating layer, a first capacitance electrode formed on the side surface of said pillar-shaped insulating member, a capacitance insulating film formed on said first capacitance electrode and a second capacitance electrode formed on said capacitance insulating film, said first insulating layer has a connection opening formed therein, and said connection opening is filled with a conductive member for connecting said first capacitance electrode and said transistor to each other.  
     
     
         2 . The semiconductor storage device as claimed in  claim 1 , wherein a second insulating layer formed of the same insulating material as said pillar-shaped insulating member of said capacitor is formed at the same height as said pillar-shaped insulating member of said capacitor on said first insulating layer in at least a part of an area other than the memory cell area containing the plural memory cells.  
     
     
         3 . The semiconductor storage device as claimed in any one of claims  1  and  2 , wherein said transistor is a MOS transistor, and the source or drain of said MOS transistor is connected to said conductive member.  
     
     
         4 . A method of manufacturing a semiconductor storage device having plural memory cells each containing a capacitor and a transistor, characterized by comprising the steps of: 
 forming the transistor on a semiconductor substrate;    forming a first insulating layer so that the transistor is covered by the first insulating layer;    forming connection openings in the first insulating layer at the positions corresponding to the respective memory cells;    filling a conductive member in each of the connection openings;    forming an insulating material layer on the first insulating layer;    subjecting the insulating material layer to a patterning treatment to form a pillar-shaped insulating member so that a part of the surface of the conductive member filled in each of the connection openings is covered by the pillar-shaped insulating member;    forming a first capacitance electrode on the side surface of the pillar-shaped insulating member;    connecting the first capacitance electrode and the conductive member to each other, forming a capacitance insulating film on the first capacitance electrode; and    forming a second capacitance electrode on the capacitance insulating film.    
     
     
         5 . The semiconductor storage device manufacturing method as claimed in  claim 4 , wherein the patterning treatment of the insulating material layer is performed by using anisotropic etching.  
     
     
         6 . The semiconductor storage device manufacturing method as claimed in  claim 4 , wherein the formation of the first capacitance electrode is performed by forming a conductive material layer and patterning the conductive material layer with anisotropic etching.  
     
     
         7 . The above semiconductor storage device manufacturing method as claimed in  claim 4 , wherein the transistor is a MOS transistor, and each connection opening is formed at the position corresponding to the source or drain of the MOS transistor.  
     
     
         8 . The semiconductor storage device manufacturing method as claimed in any one of  claims 4  to  7 , wherein the insulating material layer is also formed in an area other than the memory cell area containing the plural memory cells on the semiconductor substrate, and the insulating material layer is subjected to a patterning treatment so that a second insulating layer having the same height as the pillar-shaped insulating member of the capacitor remains in the area other than the memory cell area.