Poly-silicon thin film transistor and method for fabricating thereof

Abstract

A thin film transistor. The thin film transistor comprises a substrate, a dielectric layer and a polysilicon layer. A gate electrode is located on the substrate, A dielectric layer is located on the substrate and the gate electrode. A polysilicon layer is located on the dielectric layer. The polysilicon layer comprises a channel region and a doped region, wherein the channel region is located above the gate electrode and the doped region is adjacent to the channel region.

What is claimed is:  
     
         1 . A thin film transistor, comprising: 
 a substrate, wherein a gate electrode is located on the substrate;    a dielectric layer located on the substrate and the gate electrode; and    a polysilicon layer located on the dielectric layer, wherein the polysilicon layer comprises a channel region and a doped region, the channel region is located above the gate electrode and the doped region is adjacent to the channel region.    
     
     
         2 . The poly-silicon thin film transistor of  claim 1 , wherein the channel region is wider than the gate electrode.  
     
     
         3 . The poly-silicon thin film transistor of  claim 2 , wherein each compensation region between a margent of the doped region and the gate electrode is equal to each other.  
     
     
         4 . A method of manufacturing a thin firm transistor, comprising: 
 providing a substrate having a gate electrode formed thereon;    forming a gate dielectric layer, an amorphous silicon layer, a silicon-bond-protection layer and a photoresist layer over the substrate in sequence, wherein the silicon bond protection dielectric layer comprises elements for compensating dangling silicon bonds;    patterning the photoresist layer by using the gate electrode as a mask and by exposuring the photoresist layer form the bottom of the substrate;    processing a thermal reflow process to laterally extend the patterned photoresist, wherein the bottom of the soften photoresist is larger than the gate electrode;    removing a portion of the silicon-bond protection layer to expose a portion of the amorphous silicon layer by using the photoresist as a mask;    forming a doped dielectric layer over the substrate;    performing a thermal annealing process to convert silicon the amorphous layer into a polysilicon layer, wherein dopants in the doped doelectric layer diffuse into the polysilicon layer to form a doped region and elements in the silicon-bond-protection layer diffuse into the polysilicon layer to form a channel region; and    removing the silicon-bond-protection layer and the doped dielectric layer.    
     
     
         5 . The method of  claim 4 , wherein the thermal annealing process comprises a laser annealing process.  
     
     
         6 . The method of  claim 5 , wherein an energy of the laser annealing process is of about 100-400 mJ.  
     
     
         7 . The method of  claim 4 , wherein the silicon-bond-protection layer is made of silicon oxide fluoride.  
     
     
         8 . The method of  claim 4 , wherein the silicon bond protective dielectric layer comprises silicon hydroxide.  
     
     
         9 . The method of  claim 4 , wherein the doped dielectric layer is formed of borosilicate glass.  
     
     
         10 . The method of  claim 4 , wherein the doped dielectric layer is formed of phosphosilicate glass.  
     
     
         11 . The method of  claim 4 , wherein the thermal reflow process is performed under a temperature of about 100-250 degree Celsius.