Processing partial register writes in an out-of order processor

Abstract

A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. The instruction with an incorrectly-predicted predicate is flushed from the pipeline if the predicted value and the architecturally correct value are different.

What is claimed is:  
     
         1 . A method, comprising: 
 substantially simultaneously reading values from a plurality of registers;    parsing a particular instruction, and determining a select number of registers to be modified in the plurality of registers;    modifying a subset of the values in the select number of registers; and    substantially simultaneously writing the values to the plurality of registers.    
     
     
         2 . The method of  claim 1 , further comprising: 
 providing a means by which an entire set of values may be collectively read or collectively written by instructions that operate on the entire set of values.    
     
     
         3 . The method of  claim 2 , wherein said substantially simultaneously reading includes reading values from a plurality of predicate registers.  
     
     
         4 . The method of  claim 1 , wherein said substantially simultaneously reading includes reading values from a plurality of Not-a-Thing (NaT) registers.  
     
     
         5 . The method of  claim 1 , wherein said parsing a particular instruction includes parsing an Itanium instruction.  
     
     
         6 . The method of  claim 5 , wherein the Itanium instruction selects one register to be modified.  
     
     
         7 . The method of  claim 5 , wherein the Itanium instruction selects two registers to be modified.  
     
     
         8 . The method of  claim 5 , wherein the Itanium instruction selects 48 registers to be modified.  
     
     
         9 . The method of  claim 5 , wherein the Itanium instruction selects up to 63 registers to be modified.  
     
     
         10 . The method of  claim 1 , wherein said substantially simultaneously writing includes writing the values to a plurality of predicate registers.  
     
     
         11 . The method of  claim 10 , wherein the plurality of predicate registers includes all 63 predicate registers.  
     
     
         12 . A method, comprising: 
 providing a prediction for a predicate in an instruction;    setting a first set of values for selected predicate registers in a predicate register file according to the prediction;    obtaining a second set of values which represents determined values for the predicate, the second set of values being computed by a read-modify-write operation;    comparing the first set of values with the second set of values; and    flushing an instruction with incorrectly predicted predicate and any dependent instructions from the pipeline if the first set of values are different from the second set of values.    
     
     
         13 . The method of  claim 12 , wherein said performing a read-modify-write operation includes: 
 substantially simultaneously reading all values from all the predicate registers in the predicate register file, including the first set of values for the selected predicate registers.    
     
     
         14 . The method of  claim 13 , wherein said performing a read-modify-write operation includes: 
 parsing the instruction, and determining the selected predicate registers to be modified.    
     
     
         15 . The method of  claim 14 , wherein said performing a read-modify-write operation includes: 
 modifying the first set of values in the selected predicate registers.    
     
     
         16 . The method of  claim 15 , wherein said performing a read-modify-write operation includes: 
 substantially simultaneously writing the values to all the predicate registers in the predicate register file, including the second set of values.    
     
     
         17 . The method of  claim 12 , wherein said providing a prediction for a predicate includes providing a prediction based on history of the predicate.  
     
     
         18 . The method of  claim 12 , wherein said setting a first set of values includes setting 1, 2, 48, or up to 63 values depending on the instruction.  
     
     
         19 . The method of  claim 18 , wherein the instruction is an Itanium instruction.  
     
     
         20 . The method of  claim 12 , wherein the first set of values includes predicted values for the predicate.  
     
     
         21 . The method of  claim 12 , wherein the second set of values includes architecturally correct values for the predicate.  
     
     
         22 . The method of  claim 12 , further comprising: 
 providing a means by which an entire set of values may be collectively read or collectively written by instructions that operate on the entire set of values without a need for the read-modify-write operation.    
     
     
         23 . A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to perform a read-modify-write operation, comprising: 
 substantially simultaneously reading values from a plurality of registers;    parsing a particular instruction, and determining a select number of registers to be modified in the plurality of registers;    modifying a subset of the values in the select number of registers; and    substantially simultaneously writing the values to the plurality of registers.    
     
     
         24 . The medium of  claim 23 , wherein said substantially simultaneously reading includes reading values from a plurality of predicate registers.  
     
     
         25 . The medium of  claim 23 , further comprising: 
 providing a means by which an entire set of values may be collectively read or collectively written by instructions that operate on the entire set of values.    
     
     
         26 . A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to process registers in an out-of-order processor, comprising: 
 providing a prediction for a predicate in an instruction;    setting a first set of values for selected predicate registers in a predicate register file according to the prediction;    obtaining a second set of values which represents determined values for the predicate, the second set of values being computed by a read-modify-write operation;    comparing the first set of values with the second set of values; and    flushing an instruction with an incorrectly predicated predicate and any dependent instructions if the first set of values are different from the second set of values.    
     
     
         27 . The medium of  claim 26 , wherein said providing a prediction for a predicate includes providing a prediction based on history of the predicate.  
     
     
         28 . The medium of  claim 26 , wherein the first set of values includes predicted values for the predicate.  
     
     
         29 . The medium of  claim 26 , wherein the second set of values includes architecturally correct values for the predicate.