Semiconductor device testing apparatus having timing calibration function

Abstract

Signal propagation times TA 1, TA 2, TA 3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T 1, T 2, T 3, - - - of respective channels. The known values TA 1, TA 2, TA 3, - - - are subtracted from the measured values T 1, T 2, T 3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA 1, TA 2, TA 3, - - - and the measured values T 1, T 2, T 3 - - - become a constant value TC.

What is claimed is:  
     
         1 . A timing calibration method in a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths through which test pattern signals are transmitted to output pins and testing a semiconductor device under test using the thus transmitted test pattern signals, 
 said timing calibration method comprising the steps of: 
 selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths which are provided to correspond to the output pins, respectively;  
 measuring by means of the timing measurement device signal propagation delay time values through the respective pin selection paths and storing the measured values in a memory;  
 measuring by means of the timing measurement device total signal propagation delay time values through respective series connections each of which is constituted of one of the test pattern signal transmission paths and one of the pin selection paths corresponding to the respective output pins;  
 subtracting the memorized values of the respective pin selection paths from the corresponding total signal propagation delay time values to thereby obtain difference delay time values; and  
 adjusting delay time values of timing calibrators in the respective test pattern signal transmission paths such that those respective difference delay time values corresponding to all the output pins accord with a predetermined value whereby calibrating difference in signal propagation delay time values of the respective test pattern signal transmission paths.  
   
     
     
         2 . A timing calibration method in a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths through which test pattern signals are transmitted to output pins and testing a semiconductor device under test using the thus transmitted test pattern signals, 
 said timing calibration method comprising the steps of: 
 selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths which are provided to correspond to the output pins, respectively;  
 measuring by means of the timing measurement device signal propagation delay time values through the respective pin selection paths and storing the measured values in a memory;  
 determining one of the output pins as a reference output pin and calculating deviation values between the delay time value as a reference value through the pin selection path for the reference output pin and respective delay time values through remaining pin selection paths for remaining output pins other than the reference output pin;  
 measuring by means of the timing measurement device total signal propagation delay time vales through respective series connections each of which is constituted of one of the test pattern signal transmission paths and one of the pin selection paths  
 calculating deviation values between the total signal propagation delay time value for the reference output pin and the respective total signal propagation delay time values; and  
 adjusting signal propagation delay time values of timing calibrators in the respective test pattern signal transmission paths for the remaining output pins such that those deviation values of the total delay time values for the respective remaining output pins accord with the corresponding deviation values, respectively whereby calibrating difference in signal propagation delay time values of the respective test pattern signal transmission paths.  
   
     
     
         3 . A semiconductor device testing apparatus having a timing calibration mode comprising: 
 a pattern generator;    a pin data selector distributing pin data including test pattern data, address signals and control signals, and outputted from the pattern generator to respective pin channels corresponding to output pins waveform formatters each shaping from the pin data distributed thereto by the pin data selector a test pattern signal having a waveform that meets standard requirements of a semiconductor device under test;    timing calibrators calibrating signal propagation delay time values through respective rest pattern signal transmission paths connected to the respective waveform formatters;    drivers transmitting the test pattern signals outputted from the respective timing calibrators to the output pins to which a semiconductor device under test is coupled;    a computer system controlling operations of the testing apparatus;    a timing measurement device measuring applied timings of the test pattern signals applied to the respective output pins; and    a pin selection device connected to the output pins in a timing calibration mode and forming pin selection paths which selectively connect the respective output pins one by one to the timing measurement device; wherein 
 said computer system comprises: 
 memory means for storing therein signal propagation delay time values through the respective pin selection paths;  
 subtraction means for subtracting the stored delay time values through the respective pin selection paths from corresponding total delay time values measured by means of the timing measurement device through respective series connections of the test pattern signal transmission paths and the pin selection paths corresponding to the respective output pins; and  
 timing control means for controlling the signal propagation delay time values of the respective timing calibrators such that difference delay time values obtained as results of the subtraction means are converged to a predetermined constant value.  
 
   
     
     
         4 . A semiconductor device testing apparatus having a timing calibration mode comprising: 
 a pattern generator;    a pin data selector distributing pin data including test pattern data, address signals and control signals, and outputted from the pattern generator to respective pin channels corresponding to output pins;    waveform formatters each shaping from the pin data distributed thereto by the pin data selector a test pattern signal having a waveform that meets standard requirements of a semiconductor device under test;    timing calibrators calibrating signal propagation delay time values through respective rest pattern signal transmission paths connected to the respective waveform formatters;    drivers transmitting the test pattern signals outputted from the respective timing calibrators to the output pins to which a semiconductor device under test is coupled;    a computer system controlling operations of the testing apparatus;    a timing measurement device measuring applied timings of the test pattern signals applied to the respective output pins; and    a pin selection device connected to the output pins in a timing calibration mode and forming pin selection paths which selectively connect the respective output pins one by one to the timing measurement device; wherein 
 said computer system comprises: 
 memory means for storing therein signal propagation delay time values through the respective pin selection paths;  
 calculation means for calculating deviation values between the stored delay time value of the pin selection path stored in the memory means for one of the output pins which is determined as a reference output pin and the respective delay time values of the pin selection paths stored in the memory means for remaining output pins other than the reference output pin; and  
 timing control means for controlling the delay time values of the respective timing calibrator such that deviation values between the total signal propagation delay time value for the reference output pin and the respective total signal propagation delay time values for the remaining output pins accord with the corresponding deviation values, respectively, whereby calibrating difference in signal propagation delay time values of the respective test pattern signal transmission paths.  
 
   
     
     
         5 . A timing calibration method in a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths each constituted of a series connection of a waveform formatter, a timing calibrator, a driver and an output pin, respectively, wherein a semiconductor device under test is coupled to the output pins of the respective test pattern signal transmission paths and tested by using the test pattern signals supplied to the output pins, 
 said timing calibration method comprising the steps of:    selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths;    measuring by means of the timing measurement device signal propagation delay time values (TA 1 , TA 2 , TA 3 , - - - ) through the respective pin selection paths and storing the thus measured values in memory means;    measuring by means of the timing measurement device total signal propagation delay time values (T 1 , T 2 , T 3 , - - - ) through respective total signal paths each constituted of a series connection of each of the test pattern signal transmission paths and each of the pin selection paths corresponding to the respective output pins;    subtracting the stored signal propagation delay time values (TA 1 , TA 2 , TA 3 , - - - ) from the corresponding total signal propagation delay time values (T 1 , T 2 , T 3 , - - - ) to thereby obtain difference delay time values (TX 1 , TX 2 , TX 3 , - - - ); and    adjusting delay time values of the timing calibrators in the respective test pattern signal transmission paths such that those respective deviation delay time values (TX 1 , TX 2 , TX 3 , - - - ) for all the output pins accord with a predetermined value (TX 1 ′=TX 2 ′=TX 3 ′= - - - =TC).    
     
     
         6 . A timing calibration method in a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths each constituted of a series connection of a waveform formatter, a timing calibrator, a driver and an output pin, respectively, wherein a semiconductor device under test is coupled to the output pins of the respective test pattern signal transmission paths and tested by using the test pattern signals supplied to the output pins, 
 said timing calibration method comprising the steps of: 
 selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths;  
 measuring by means of the timing measurement device signal propagation delay time values (TA 1 , TA 2 , TA 3 , - - - ) through the respective pin selection paths and storing the thus measured values in memory means;  
 determining one of the output pins as a reference output pin;  
 calculating deviation values (ΔT 1 =TA 2 −TA 1 , ΔT 2 =TA 3 −TA 1 , - - - ) between the delay time value (TA 1 ) as a reference value through the pin selection path for the reference output pin and the respective delay time values (TA 2 , TA 3 , - - - ) through remaining pin selection paths for the remaining output pins other than the reference output pin; and  
 adjusting delay time values (TX 1 , TX 2 , - - - ) of the timing calibrators in the respective test pattern signal transmission paths such that those respective deviation delay time values (T 2 −T 1 , T 3 −T 1 , - - - ) between the total signal propagation delay time value (T 1 ) through a total signal path which is constituted of a series connection of the test pattern signal transmission path and the pin selection path for the reference output pin and the respective total signal propagation delay time values (T 2 , T 3 , - - - ) through respective total signal paths which are constituted of series connections of the test pattern signal transmission paths and the pin selection paths for remaining output pins other than the reference output pin, accord with the corresponding deviation delay time values (ΔT 1 =T 2 −T 1 , ΔT 2 =T 3 −T 1 , - - - ) through the respective pin selection paths for the remaining output pins, respectively.  
   
     
     
         7 . A semiconductor device testing apparatus wherein a semiconductor device under test coupled to output pins is tested by using test pattern signals transmitted to the output pins, said testing apparatus comprising: 
 a plurality of test pattern signal transmission paths each constituted of a series connection of a waveform formatter, a timing calibrator, a driver and one of the output pins, respectively,    a computer system controlling operations of the testing apparatus;    a timing measurement device used for timing calibration mode; and    a pin selection device used for timing calibration mode and forming pin selection paths which selectively connect the output pins one by one to the timing measurement device, wherein    said timing measurement device measures total signal propagation delay time values (T 1 , T 2 , - - - ) of timing calibration pulse signals transmitted through respective series connections of one of the respective signal transmission paths and one of the respective pin selection paths for the respective output pins,    said computer system includes: 
 memory means for storing therein delay time values (TA 1 , TA 2 , - - - ) of the timing calibration pulse signal transmitted through the respective pin selection paths;  
 subtract means for subtracting the stored delay time values (TA 1 , TA 2 , - - - ) through the respective pin selection paths stored in the memory means from the corresponding measured total delay time values (T 1 , T 2 , - - - ) through the respective pin channels; and  
   timing control means for controlling the delay time values of respective timing calibrators such that difference delay time values (TX 1 , TX 2 , - - - ) for the respective output pins obtained as results of the subtract means are converged to a same predetermined constant value (TX 1 ′, TX 2 ′, - - - ,=TC).    
     
     
         8 . A semiconductor device testing apparatus wherein a semiconductor device under test coupled to output pins is tested by using test pattern signals transmitted to the output pins, said testing apparatus comprising: 
 a plurality of test pattern signal transmission paths each constituted of a series connection of a waveform formatter, a timing calibrator, a driver and one of the output pins, respectively,    a computer system controlling operations of the testing apparatus;    a timing measurement device used for timing calibration mode; and    a pin selection device used for timing calibration mode and forming pin selection paths which selectively connect the output pins one by one to the timing measurement device, wherein 
 said timing measurement device measures total signal propagation delay time values (T 1 , T 2 , - - - ) of timing calibration pulse signals transmitted through respective series connections of one of the respective signal transmission paths and one of the respective pin selection paths for the respective output pins,,  
 said computer system includes: 
 memory means for storing therein delay time values (TA 1 , TA 2 , - - - ) of the timing calibration pulse signal transmitted through the respective pin selection paths;  
 calculating deviation values (ΔT 1 , ΔT 2 , - - - ) between the stored delay time value (TA 1 ) for one of the output pins determined as a reference output pin and respective stored delay time values (TA 2 , TA 3 , - - - ) through remaining pin selection paths for the remaining output pins other than the reference output pin; and  
 timing control means for adjusting delay time values of the respective timing calibrators such that those respective deviation delay time values (T 2 −T 1 , T 3 −T 1 , - - - ) between the total signal propagation delay time value (T 1 ) through a total signal path which is constituted of a series connection of the test pattern signal transmission path and the pin selection path for the reference output pin and the respective total signal propagation delay time values (T 2 , T 3 , - - - ) through respective total signal paths which are constituted of series connections of the test pattern signal transmission paths and the pin selection paths for remaining output pins other than the reference output pin, accord with the corresponding deviation delay time values (ΔT 1 =T 2 −T 1 , ΔT 2 =T 3 −T 1 , - - - ) through the respective pin selection paths for the remaing output pins, respectively.