Fabrication method for semiconductor integrated circuit device

Abstract

For carrying out chemical mechanical polishing while supplying a polishing slurry to a surface of individual wafers running through a mass-production process so as to suppress the occurrence of microscratches by reducing the density of coagulated particles in the polishing slurry used in a chemical mechanical polishing step, the polishing slurry used is allowed to stand in a container for at least 30 days or more, preferably 40 days or more, and more preferably 50 days or more, so that the concentration of coagulated particles having a size of 1 μm or more is at 200,000 particles/0.5 cc, preferably 50,000 particles/0.5 cc, and more preferably 20,000 particles/0.5 cc.

What is claimed is:  
     
         1 . A method for manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) allowing a polishing slurry used for chemical mechanical polishing to stand so that a concentration of coagulated particles having a size of 1 μm or over in said polishing slurry is at 200,000 particles/0.5 cc or below; and    (b) subjecting a surface to be processed of individual wafers running through a mass-production process to chemical mechanical polishing while supplying said polishing slurry obtained after the step (a) to said surface.    
     
     
         2 . A method for manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the concentration of the coagulated particles having a size of 1 μm or below in said polishing slurry is at 50,000 particles/0.5 cc or below.  
     
     
         3 . A method for manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the concentration of the coagulated particles having a size of 1 μm or below in said polishing slurry is at 20,000 particles/0.5 cc or below.  
     
     
         4 . A method for manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein said coagulated particles are mainly made of silica.  
     
     
         5 . A method for manufacturing a semiconductor integrated circuit device according to  claim 4 , wherein said silica is mainly made of fumed silica.  
     
     
         6 . A method for manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the chemical mechanical polishing step is a step of forming a polished, planarized insulating film isolation groove in a main surface of said individual wafers.  
     
     
         7 . A method for manufacturing a semiconductor integrated circuit device according to  claim 1 , wherein the concentration of said coagulated particles having a size of 1 μm or below is determined by measuring a size of coagulated particles contained in said polishing slurry.  
     
     
         8 . A method for manufacturing a semiconductor integrated circuit device according to  claim 1 , further comprising filtering said polishing slurry after the step (a) and prior to the step (b).  
     
     
         9 . A method for fabricating a semiconductor integrated circuit device comprising the steps of: 
 (a) allowing a polishing slurry used for chemical mechanical polishing to stand for 30 days or over; and    (b) subjecting a surface to be processed of individual wafers running through a mass-production process to chemical mechanical polishing while supplying said polishing slurry obtained after the step (a) to said surface.    
     
     
         10 . A method for manufacturing a semiconductor integrated circuit device according to  claim 9 , wherein said polishing slurry is allowed to stand for 40 days or over.  
     
     
         11 . A method for manufacturing a semiconductor integrated circuit device according to  claim 9 , wherein said polishing slurry is allowed to stand for 45 days or over.  
     
     
         12 . A method for manufacturing a semiconductor integrated circuit device according to  claim 9 , wherein the chemical mechanical polishing step is a step of forming a polished, planarized insulating film isolation groove in a main surface of said individual wafers.  
     
     
         13 . A method for manufacturing a semiconductor integrated circuit device according to  claim 9 , wherein said coagulated particles are mainly made of silica.  
     
     
         14 . A method for fabricating a semiconductor integrated circuit device comprising the steps of: 
 (a) forming a groove in an element isolation region over a main surface of a wafer by etching said element isolation region over the main surface of the wafer by use, as a mask, of an oxidation-resistant insulating film formed over the main surface of said water;    (b) forming a silicon oxide insulating film over the main surface of said wafer including the inside of the groove; and    (c) subjecting said silicon oxide insulating film to chemical mechanical polishing through said oxidation-resistant insulating film as a stopper for polishing so that said silicon oxide insulating film is selectively left inside the groove thereby forming a polished, planarized insulating film isolation groove in said element isolation region on the main surface of said wafer,    wherein when said silicon oxide insulating film is subjected to chemical mechanical polishing, a polishing slurry obtained after allowing to stand until a concentration of coagulated particles having a size of 1 μm or over is at 200,000 particles/0.5 cc of the slurry or below is used.    
     
     
         15 . A method for fabricating a semiconductor integrated circuit device according to  claim 14 , wherein said polishing slurry is allowed to stand until the concentration of the coagulated particles having a size of 1 μm or over is at 50,000 particles/0.5 cc.  
     
     
         16 . A method for fabricating a semiconductor integrated circuit device according to  claim 14 , wherein said polishing slurry is allowed to stand until the concentration of the coagulated particles having a size of 1 μm or over is at 20,000 particles/0.5 cc.  
     
     
         17 . A method for fabricating a semiconductor integrated circuit device according to  claim 14 , wherein the concentration of said coagulated particles having a size of 1 μm or below is determined by measuring a size of coagulated particles contained in said polishing slurry.  
     
     
         18 . A method for fabricating a semiconductor integrated circuit device according to  claim 14 , wherein said coagulated particles are mainly made of silica.  
     
     
         19 . A method for fabricating a semiconductor integrated circuit device comprising the steps of: 
 (a) forming a groove in an element isolation region over a main surface of a wafer by etching said element isolation region over the main surface of said wafer by use, as a mask, of an oxidation-resistant insulating film formed over the main surface of said water;    (b) forming a silicon oxide insulating film over the main surface of said wafer including the inside of said groove; and    (c) subjecting said silicon oxide insulating film to chemical mechanical polishing through said oxidation-resistant insulating film as a stopper for polishing so that said silicon oxide insulating film is selectively left inside the groove thereby forming a polished, planarized insulating film isolation groove in said element isolation region over the main surface of said wafer,    wherein when the silicon oxide insulating film is subjected to chemical mechanical polishing, a polishing slurry obtained after allowing to stand for 30 days or over is used.    
     
     
         20 . A method for fabricating a semiconductor integrated circuit device according to  claim 19 , wherein said polishing slurry is allowed to stand for 40 days or over.  
     
     
         21 . A method for fabricating a semiconductor integrated circuit device according to  claim 20 , wherein said polishing slurry is allowed to stand for 45 days or over.  
     
     
         22 . A method for fabricating a semiconductor integrated circuit device according to  claim 19 , wherein said coagulated particles are mainly made of silica.  
     
     
         23 . A method for manufacturing a semiconductor integrated circuit device comprising the steps of: 
 (a) allowing a polishing slurry used for chemical mechanical polishing to stand so that a concentration of coagulated particles having a size of 1 μm or over in said polishing slurry is at 200,000 particles/0.5 cc or below; and    (b) subjecting a surface to be processed of individual wafers running through a mass-production process to chemical mechanical polishing while supplying said polishing slurry obtained after the step (a) to said surface.    
     
     
         24 . A method for fabricating a semiconductor integrated circuit device according to  claim 23 , wherein the concentration of the coagulated particles having a size of 1 μm or over in said polishing slurry is at 50,000 particles/0.5 cc or below.  
     
     
         25 . A method for fabricating a semiconductor integrated circuit device according to  claim 24 , wherein the concentration of the coagulated particles having a size of 1 μm or over in said polishing slurry is at 20,000 particles/0.5 cc or below.  
     
     
         26 . A method for fabricating a semiconductor integrated circuit device according to  claim 23 , wherein said polishing slurry is allowed to stand for 30 days or over.  
     
     
         27 . A method for fabricating a semiconductor integrated circuit device according to  claim 26 , wherein said polishing slurry is allowed to stand for 40 days or over.  
     
     
         28 . A method for fabricating a semiconductor integrated circuit device according to  claim 27 , wherein said polishing slurry is allowed to stand for 45 days or over.  
     
     
         29 . A method for fabricating a semiconductor integrated circuit device according to  claim 23 , wherein said coagulated particles are mainly made of silica.